/external/libedit/src/ |
H A D | keymacro.c | 628 #define ADDC(c) \ macro 644 ADDC(sep[0]); 647 ADDC('^'); 648 ADDC('@'); 665 ADDC(sep[1]); 667 ADDC('\0');
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 193 /// like ADDC/SUBC, which indicate the carry result is always false. 200 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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H A D | SelectionDAG.h | 1035 case ISD::ADDC:
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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H A D | MipsSEISelDAGToDAG.cpp | 237 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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H A D | MipsSEISelLowering.cpp | 389 // ADDENode's second operand must be a flag output of an ADDC node in order 393 if (ADDCNode->getOpcode() != ISD::ADDC)
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/external/pcre/dist/sljit/ |
H A D | sljitNativeSPARC_32.c | 100 return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
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H A D | sljitNativePPC_32.c | 119 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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H A D | sljitNativePPC_64.c | 240 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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H A D | sljitNativeSPARC_common.c | 119 #define ADDC (OPC1(0x2) | OPC3(0x08)) macro
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand); 214 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand); 214 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 205 case ISD::ADDC: return "addc";
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H A D | LegalizeIntegerTypes.cpp | 1200 case ISD::ADDC: 1343 TLI.isOperationLegalOrCustom(ISD::ADDC, 1348 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps); 1586 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1588 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1593 ISD::ADDC : ISD::SUBC, 1599 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); 1647 if (N->getOpcode() == ISD::ADDC) { 1648 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
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H A D | DAGCombiner.cpp | 1200 case ISD::ADDC: return visitADDC(N); 1668 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0); 1708 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); 2944 APInt ADDC = ADDI->getAPIntValue(); local 2945 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2954 ADDC |= Mask; 2955 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2958 N0.getOperand(0), DAG.getConstant(ADDC, VT));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 77 ADDC, // Add with carry enumerator in enum:llvm::ARMISD::NodeType
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H A D | ARMISelLowering.cpp | 580 setTargetDAGCombine(ISD::ADDC); 630 setOperationAction(ISD::ADDC, MVT::i32, Custom); 969 case ARMISD::ADDC: return "ARMISD::ADDC"; 6064 case ISD::ADDC: Opc = ARMISD::ADDC; break; 6243 case ISD::ADDC: 7802 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by 7807 // ADDC | hiAdd 7812 assert(AddcNode->getOpcode() == ISD::ADDC [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1393 setOperationAction(ISD::ADDC, MVT::i8, Expand); 1394 setOperationAction(ISD::ADDC, MVT::i16, Expand); 1395 setOperationAction(ISD::ADDC, MVT::i32, Expand); 1396 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1458 setOperationAction(ISD::ADDC, MVT::i64, Custom); 2692 case ISD::ADDC: hiOpc = ISD::ADDE; break; 2825 case ISD::ADDC:
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 221 setOperationAction(ISD::ADDC, MVT::i32, Custom); 225 setOperationAction(ISD::ADDC, MVT::i64, Custom); 1279 case ISD::ADDC: 1546 case ISD::ADDC:
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 78 setOperationAction(ISD::ADDC, MVT::i32, Legal);
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H A D | AMDGPUISelLowering.cpp | 312 setOperationAction(ISD::ADDC, VT, Expand);
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H A D | R600ISelLowering.cpp | 175 setOperationAction(ISD::ADDC, VT, Expand);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 95 setOperationAction(ISD::ADDC, MVT::i32, Expand);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 222 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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