Searched refs:ADDiu (Results 1 - 12 of 12) sorted by relevance

/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
56 // A single ADDiu will do if RemSize <= 16.
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
79 // Replace a ADDiu & SLL pair with a LUi.
81 // ADDiu 0x0111
86 // Check if the first two instructions are ADDiu and SLL and the shift amount
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
92 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
130 ADDiu
[all...]
H A DMipsAnalyzeImmediate.h26 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
35 /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
H A DMipsSERegisterInfo.cpp165 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
168 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; local
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
H A DMipsLongBranch.cpp293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
298 // LUi and ADDiu instructions create 32-bit offset of the target basic
307 // we replace LUi and ADDiu with pseudo instructions
310 // instructions to LUi and ADDiu in the MC layer, we will create
333 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
443 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
H A DMipsMCInstLower.cpp202 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
H A DMipsSEISelDAGToDAG.cpp90 if ((MI.getOpcode() == Mips::ADDiu) &&
169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
185 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
702 // instructions (ADDiu, ORI and SLL) in that it does not have a register
H A DMipsSEInstrInfo.cpp366 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; local
369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
399 // instructions (ADDiu, ORI and SLL) in that it does not have a register
H A DMipsFastISel.cpp375 unsigned Opc = Mips::ADDiu;
H A DMipsSEISelLowering.cpp2776 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2782 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2843 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2849 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
H A DMipsISelLowering.cpp1138 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1378 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp559 TmpInst.setOpcode(Mips::ADDiu);
618 Inst.setOpcode(Mips::ADDiu);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1100 tmpInst.setOpcode(Mips::ADDiu);
1188 tmpInst.setOpcode(Mips::ADDiu);
1230 tmpInst.setOpcode(Mips::ADDiu);

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