/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUTargetMachine.h | 36 AMDGPUTargetLowering * TLInfo; 58 virtual AMDGPUTargetLowering * getTargetLowering() const {
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H A D | AMDGPUISelLowering.cpp | 23 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : function in class:AMDGPUTargetLowering 48 SDValue AMDGPUTargetLowering::LowerFormalArguments( 64 SDValue AMDGPUTargetLowering::LowerReturn( 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 101 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 149 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, 163 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, 180 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, 291 bool AMDGPUTargetLowering [all...] |
H A D | R600ISelLowering.h | 23 class R600TargetLowering : public AMDGPUTargetLowering
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H A D | AMDILISelLowering.cpp | 47 void AMDGPUTargetLowering::InitAMDILLowering() 243 AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 250 AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const 261 AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const 277 AMDGPUTargetLowering::computeMaskedBitsForTargetNode( 317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const 335 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const 354 AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const 420 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const 451 AMDGPUTargetLowering [all...] |
H A D | SIISelLowering.h | 22 class SITargetLowering : public AMDGPUTargetLowering
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H A D | AMDGPUISelLowering.h | 24 class AMDGPUTargetLowering : public TargetLowering class in namespace:llvm 42 AMDGPUTargetLowering(TargetMachine &TM);
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H A D | SIISelLowering.cpp | 27 AMDGPUTargetLowering(TM), 79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 443 default: return AMDGPUTargetLowering::getTargetNodeName(Opcode);
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H A D | R600ISelLowering.cpp | 26 AMDGPUTargetLowering(TM), 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 280 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUTargetMachine.h | 33 std::unique_ptr<AMDGPUTargetLowering> TLInfo; 56 AMDGPUTargetLowering *getTargetLowering() const override {
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H A D | AMDGPUISelLowering.cpp | 88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { 98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { 106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : function in class:AMDGPUTargetLowering 389 MVT AMDGPUTargetLowering::getVectorIdxTy() const { 393 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { 399 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 405 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { 410 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, 427 bool AMDGPUTargetLowering [all...] |
H A D | AMDGPUTargetTransformInfo.cpp | 42 const AMDGPUTargetLowering *TLI;
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H A D | R600ISelLowering.h | 24 class R600TargetLowering : public AMDGPUTargetLowering {
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H A D | SIISelLowering.h | 23 class SITargetLowering : public AMDGPUTargetLowering {
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H A D | AMDGPUISelLowering.h | 27 class AMDGPUTargetLowering : public TargetLowering { class in namespace:llvm 105 AMDGPUTargetLowering(TargetMachine &TM);
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H A D | SIISelLowering.cpp | 32 AMDGPUTargetLowering(TM) { 467 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 604 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 642 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 844 SDValue Lowered = AMDGPUTargetLowering::LowerLOAD(Op, DAG); 940 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG); 1116 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); 1177 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); 1716 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
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H A D | R600ISelLowering.cpp | 33 AMDGPUTargetLowering(TM), 211 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 571 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 628 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 840 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); 1350 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG); 1411 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG); 1506 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG); 1837 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); 1952 SDValue Ret = AMDGPUTargetLowering [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 780 const AMDGPUTargetLowering& Lowering = 781 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUTargetMachine.h | 36 AMDGPUTargetLowering * TLInfo; 58 virtual AMDGPUTargetLowering * getTargetLowering() const {
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H A D | AMDGPUISelLowering.cpp | 23 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : function in class:AMDGPUTargetLowering 48 SDValue AMDGPUTargetLowering::LowerFormalArguments( 64 SDValue AMDGPUTargetLowering::LowerReturn( 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 101 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 149 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, 163 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, 180 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, 291 bool AMDGPUTargetLowering [all...] |
H A D | R600ISelLowering.h | 23 class R600TargetLowering : public AMDGPUTargetLowering
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H A D | AMDILISelLowering.cpp | 47 void AMDGPUTargetLowering::InitAMDILLowering() 243 AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 250 AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const 261 AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const 277 AMDGPUTargetLowering::computeMaskedBitsForTargetNode( 317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const 335 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const 354 AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const 420 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const 451 AMDGPUTargetLowering [all...] |
H A D | SIISelLowering.h | 22 class SITargetLowering : public AMDGPUTargetLowering
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H A D | AMDGPUISelLowering.h | 24 class AMDGPUTargetLowering : public TargetLowering class in namespace:llvm 42 AMDGPUTargetLowering(TargetMachine &TM);
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H A D | SIISelLowering.cpp | 27 AMDGPUTargetLowering(TM), 79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 443 default: return AMDGPUTargetLowering::getTargetNodeName(Opcode);
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H A D | R600ISelLowering.cpp | 26 AMDGPUTargetLowering(TM), 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 280 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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