| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 522 /// BRCOND - Conditional branch. The first operand is the chain, the
526 BRCOND, enumerator in enum:llvm::ISD::NodeType
|
| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 139 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
605 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
765 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, argument
768 SDLoc DL(BRCOND);
770 SDNode *Intr = BRCOND.getOperand(1).getNode();
771 SDValue Target = BRCOND.getOperand(2);
784 BR = findUser(BRCOND, ISD::BR);
797 Ops.push_back(BRCOND.getOperand(0));
811 BRCOND.getOperand(2)
|
| H A D | R600ISelLowering.cpp | 71 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
589 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUISelLowering.cpp | 93 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
| H A D | AMDILISelLowering.cpp | 115 setOperationAction(ISD::BRCOND, VT, Custom);
215 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 40 BRCOND, // Conditional branch instruction; "b.cond". enumerator in enum:llvm::AArch64ISD::__anon25945
|
| H A D | AArch64ISelLowering.cpp | 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
654 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
2876 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2933 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2946 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2949 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
7738 case AArch64ISD::BRCOND:
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUISelLowering.cpp | 93 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
| H A D | AMDILISelLowering.cpp | 115 setOperationAction(ISD::BRCOND, VT, Custom);
215 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 261 case ISD::BRCOND: return "brcond";
|
| H A D | SelectionDAGBuilder.cpp | 1710 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1781 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1835 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1916 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1974 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
2129 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
|
| H A D | DAGCombiner.cpp | 1260 case ISD::BRCOND: return visitBRCOND(N);
4437 // itself may not be optimized further. Look for it and add the BRCOND into
4441 if (Use->getOpcode() == ISD::BRCOND)
4446 if (Use->getOpcode() == ISD::BRCOND)
7426 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
7471 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7502 return DAG.getNode(ISD::BRCOND, SDLoc(N),
|
| H A D | LegalizeIntegerTypes.cpp | 810 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
|
| H A D | LegalizeDAG.cpp | 3923 case ISD::BRCOND:
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 47 BRCOND, // Conditional branch. enumerator in enum:llvm::ARMISD::NodeType
|
| H A D | ARMISelLowering.cpp | 791 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
942 case ARMISD::BRCOND: return "ARMISD::BRCOND";
3607 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3639 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3661 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3665 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
|
| H A D | ARMISelDAGToDAG.cpp | 2676 case ARMISD::BRCOND: {
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 128 BRCOND, enumerator in enum:llvm::X86ISD::NodeType
|
| H A D | X86ISelLowering.cpp | 450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
11637 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12966 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12997 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13042 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13072 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13106 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16209 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16509 case X86ISD::BRCOND: return "X86ISD::BRCOND";
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 108 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 253 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
784 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
|
| H A D | MipsSEISelLowering.cpp | 188 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1443 // Sparc doesn't have BRCOND either, it has BR_CC.
1444 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 140 // Expand BRCOND into a BR_CC (see above).
141 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 246 // PowerPC does not have BRCOND which requires SetCC
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
645 setTargetDAGCombine(ISD::BRCOND);
8370 case ISD::BRCOND: {
|