/external/llvm/include/llvm/Analysis/ |
H A D | TargetTransformInfo.h | 267 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, 277 virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
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/external/llvm/lib/Analysis/ |
H A D | TargetTransformInfo.cpp | 103 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, argument 107 return PrevTTI->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, 111 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, argument 115 return PrevTTI->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, 494 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, 499 return !BaseGV && BaseOffset == 0 && Scale <= 1; 502 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, 505 if(isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale))
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/external/llvm/lib/CodeGen/ |
H A D | BasicTargetTransformInfo.cpp | 81 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, 84 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, 148 bool BasicTTI::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, argument 152 AM.BaseGV = BaseGV; 159 int BasicTTI::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, argument 163 AM.BaseGV = BaseGV;
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H A D | CodeGenPrepare.cpp | 1048 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && 1063 if (BaseGV) { 1066 BaseGV->printAsOperand(OS, /*PrintType=*/false); 2198 if (!AddrMode.BaseGV) { 2199 AddrMode.BaseGV = GV; 2202 AddrMode.BaseGV = nullptr; 2624 if (AddrMode.BaseGV) { 2628 ResultPtr = AddrMode.BaseGV; 2770 // Add in the BaseGV i [all...] |
H A D | TargetLoweringBase.cpp | 1438 if (AM.BaseGV)
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 40 // TODO: Should the addressing mode BaseGV be changed to a ConstantExpr instead 229 GlobalValue *BaseGV; member in struct:__anon26297::Formula 262 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0), 423 BaseGV ? BaseGV->getType() : 456 if (BaseGV) { 458 BaseGV->printAsOperand(OS, /*PrintType=*/false); 1033 if (F.BaseGV) 1384 GlobalValue *BaseGV, int64_t BaseOffset, 1388 return TTI.isLegalAddressingMode(AccessTy, BaseGV, BaseOffse 1382 isAMCompletelyFolded(const TargetTransformInfo &TTI, LSRUse::KindType Kind, Type *AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument 1436 isAMCompletelyFolded(const TargetTransformInfo &TTI, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument 1474 isLegalUse(const TargetTransformInfo &TTI, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument 1540 isAlwaysFoldable(const TargetTransformInfo &TTI, LSRUse::KindType Kind, Type *AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg) argument 1572 GlobalValue *BaseGV = ExtractSymbol(S, SE); local [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 1243 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1244 /// If BaseGV is null, there is no BaseGV. 1250 GlobalValue *BaseGV; 1254 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1639 if (AM.BaseGV) {
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1917 if (AM.BaseGV) {
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2561 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 2569 if (AM.BaseGV) {
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 3220 if (AM.BaseGV)
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 357 if (AM.BaseGV)
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 16653 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) 16656 if (AM.BaseGV) { 16658 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 16664 // If BaseGV requires a register for the PIC base, we cannot also have a
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 6200 if (AM.BaseGV)
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 9938 if (AM.BaseGV)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8753 if (AM.BaseGV)
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