Searched refs:BaseReg (Results 1 - 25 of 41) sorted by relevance

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/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp148 unsigned BaseReg; local
150 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
151 if (PrevBaseReg == BaseReg) {
160 PrevBaseReg = BaseReg;
H A DAArch64RegisterInfo.h78 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
81 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DAArch64LoadStoreOptimizer.cpp396 unsigned BaseReg = FirstMI->getOperand(1).getReg(); local
404 if (FirstMI->modifiesRegister(BaseReg, TRI))
439 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
513 if (ModifiedRegs[BaseReg])
606 static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg, argument
625 if (MI->getOperand(0).getReg() == BaseReg &&
626 MI->getOperand(1).getReg() == BaseReg &&
647 unsigned BaseReg = MemMI->getOperand(1).getReg(); local
653 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestRe
702 unsigned BaseReg = MemMI->getOperand(1).getReg(); local
[all...]
H A DAArch64RegisterInfo.cpp283 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
286 unsigned BaseReg,
297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
306 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
315 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
285 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp214 unsigned DestReg, unsigned BaseReg, int NumBytes,
217 if (NumBytes == 0 && DestReg != BaseReg) {
219 .addReg(BaseReg, RegState::Kill)
229 if (DestReg != ARM::SP && DestReg != BaseReg &&
251 .addReg(BaseReg, RegState::Kill)
258 .addReg(BaseReg, RegState::Kill)
269 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
272 .addReg(BaseReg).setMIFlags(MIFlags));
273 BaseReg = ARM::SP;
278 if (BaseReg
212 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DThumb1RegisterInfo.cpp91 unsigned DestReg, unsigned BaseReg,
98 (BaseReg != 0 && !isARMLowRegister(BaseReg));
110 assert(BaseReg == ARM::SP && "Unexpected!");
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
168 unsigned DestReg, unsigned BaseReg,
184 if (DestReg == BaseReg && BaseReg == ARM::SP) {
190 } else if (!isSub && BaseReg
88 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
165 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
[all...]
H A DThumb1RegisterInfo.h50 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DARMBaseRegisterInfo.h151 unsigned BaseReg, int FrameIdx,
153 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DARMBaseRegisterInfo.cpp577 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
581 unsigned BaseReg, int FrameIdx,
596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
605 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
624 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
627 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
580 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
H A DARMLoadStoreOptimizer.cpp1363 unsigned BaseReg, bool BaseKill, bool BaseUndef,
1371 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1377 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1389 unsigned BaseReg = BaseOp.getReg(); local
1396 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
1426 .addReg(BaseReg, getKillRegState(BaseKill))
1433 .addReg(BaseReg, getKillRegState(BaseKill))
1457 (TRI->regsOverlap(EvenReg, BaseReg))) {
1458 assert(!TRI->regsOverlap(OddReg, BaseReg));
1461 BaseReg, fals
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1875 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
2037 unsigned BaseReg = 0, PredReg = 0; local
[all...]
H A DThumb2SizeReduction.cpp418 unsigned BaseReg = MI->getOperand(0).getReg(); local
419 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
426 if (MI->getOperand(i).getReg() == BaseReg) {
440 unsigned BaseReg = MI->getOperand(1).getReg(); local
441 if (BaseReg != ARM::SP)
454 unsigned BaseReg = MI->getOperand(1).getReg(); local
455 if (BaseReg == ARM::SP &&
460 } else if (!isARMLowRegister(BaseReg) ||
H A DARMBaseInstrInfo.h402 unsigned DestReg, unsigned BaseReg, int NumBytes,
408 unsigned DestReg, unsigned BaseReg, int NumBytes,
413 unsigned DestReg, unsigned BaseReg,
/external/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp327 unsigned BaseReg = 0; local
365 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
392 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
394 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
400 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
411 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
415 TRI->resolveFrameIndex(*I, BaseReg, Offset);
H A DCodeGenPrepare.cpp1040 Value *BaseReg; member in struct:__anon25735::ExtAddrMode
1042 ExtAddrMode() : BaseReg(nullptr), ScaledReg(nullptr) {}
1047 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
1076 if (BaseReg) {
1079 BaseReg->printAsOperand(OS, /*PrintType=*/false);
2106 AddrMode.BaseReg = AddrInst->getOperand(0);
2119 AddrMode.BaseReg = AddrInst->getOperand(0);
2242 AddrMode.BaseReg = Addr;
2247 AddrMode.BaseReg
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp253 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon26165::X86AsmParser::IntelExprStateMachine
262 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
266 unsigned getBaseReg() { return BaseReg; }
355 // If we already have a BaseReg, then assume this is the IndexReg with
357 if (!BaseReg) {
358 BaseReg = TmpReg;
360 assert (!IndexReg && "BaseReg/IndexReg already set!");
392 // If we already have a BaseReg, then assume this is the IndexReg with
394 if (!BaseReg) {
395 BaseReg
772 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
978 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1245 int BaseReg = SM.getBaseReg(); local
1770 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
[all...]
H A DX86Operand.h52 unsigned BaseReg; member in struct:llvm::X86Operand::MemOp
113 return Mem.BaseReg;
449 Res->Mem.BaseReg = 0;
461 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, argument
467 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
475 Res->Mem.BaseReg = BaseReg;
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h94 unsigned BaseReg, int FrameIdx,
96 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DPPCRegisterInfo.cpp940 /// Insert defining instruction(s) for BaseReg to
944 unsigned BaseReg, int FrameIdx,
957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
959 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
963 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
972 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
982 MRI.constrainRegClass(BaseReg,
943 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp186 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
201 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
208 if (IndexReg.getReg() || BaseReg.getReg()) {
210 if (BaseReg.getReg())
H A DX86IntelInstPrinter.cpp166 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
181 if (BaseReg.getReg()) {
200 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/llvm/lib/Target/X86/
H A DX86CodeEmitter.cpp482 unsigned BaseReg = Base.getReg();
485 if (BaseReg == X86::RIP ||
500 // If no BaseReg, issue a RIP relative instruction only if the MCE can
504 if (BaseReg != 0 && BaseReg != X86::RIP)
505 BaseRegNo = getX86RegNum(BaseReg);
515 (!Is64BitMode || BaseReg != 0)) {
516 if (BaseReg == 0 || // [disp32] in X86-32 mode
517 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
551 if (BaseReg
[all...]
H A DX86AsmPrinter.cpp235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
240 bool HasBaseReg = BaseReg.getReg() != 0;
242 BaseReg.getReg() == X86::RIP)
300 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
315 if (BaseReg.getReg()) {
333 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
249 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
252 if ((BaseReg.getReg() != 0 &&
253 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
264 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
267 if ((BaseReg.getReg() != 0 &&
268 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg
395 unsigned BaseReg = Base.getReg(); local
[all...]
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); local
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
/external/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp550 unsigned BaseReg = 0; local
552 if (ParseRegister(BaseReg, S, E)) {
562 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E));
578 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
579 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));

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