Searched refs:CPSR (Results 1 - 21 of 21) sorted by relevance

/external/chromium_org/v8/src/arm/
H A Dconstants-arm.h222 CPSR = 0 << 22, enumerator in enum:v8::internal::SRegister
245 CPSR_c = CPSR | 1 << 16,
246 CPSR_x = CPSR | 1 << 17,
247 CPSR_s = CPSR | 1 << 18,
248 CPSR_f = CPSR | 1 << 19,
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp53 // 2 - Always set CPSR.
184 // Last instruction to define CPSR in the current block.
186 // Was CPSR last defined by a high latency instruction?
187 // When CPSRDef is null, this refers to CPSR defs in predecessors.
215 if (*Regs == ARM::CPSR)
231 /// the 's' 16-bit instruction partially update CPSR. Abort the
232 /// transformation to avoid adding false dependency on last CPSR setting
236 /// last instruction that defines the CPSR and the current instruction. If there
238 /// before the CPSR setting instruction anyway.
263 if (Reg == 0 || Reg == ARM::CPSR)
[all...]
H A DARMMCInstLower.cpp73 // Ignore all non-CPSR implicit register operands.
74 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
H A DThumb2ITBlockPass.cpp88 if (Reg == ARM::CPSR)
126 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DARMFastISel.cpp216 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
229 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
230 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { argument
234 // Look to see if our OptionalDef is defining CPSR or CCR.
238 if (MO.getReg() == ARM::CPSR)
239 *CPSR = true;
262 // CPSR defs that need to be added before the remaining operands. See s_cc_out
275 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
276 bool CPSR local
[all...]
H A DARMBaseInstrInfo.cpp511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
512 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
548 if (MO.getReg() != ARM::CPSR)
553 // all definitions of CPSR are dead
1667 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1697 // predicated instructions which will be reading CPSR.
1731 // 4: CPSR use.
1778 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1796 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1799 /// This will go away once we can teach tblgen how to set the optional CPSR de
[all...]
H A DARMBaseInstrInfo.h339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
394 /// CPSR def operand.
H A DARMAsmPrinter.cpp1626 .addReg(ARM::CPSR)
1645 .addReg(ARM::CPSR)
1660 .addReg(ARM::CPSR)
H A DARMISelLowering.cpp3283 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3313 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3453 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3494 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3606 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3638 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3658 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4025 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4059 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
6372 .addReg(ARM::CPSR, RegStat
[all...]
H A DARMExpandPseudoInsts.cpp912 .addReg(ARM::CPSR, RegState::Define);
1076 .addReg(ARM::CPSR, RegState::Undef);
H A DARMCodeEmitter.cpp774 // Encode S bit if MI modifies CPSR.
799 // Encode S bit if MI modifies CPSR.
993 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1010 // Encode S bit if MI modifies CPSR.
1311 // Encode S bit if MI modifies CPSR.
H A DARMConstantIslandPass.cpp1790 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1792 if (!Br.MI->killsRegister(ARM::CPSR))
H A DARMFrameLowering.cpp1889 .addReg(ARM::CPSR);
H A DARMLoadStoreOptimizer.cpp784 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
785 // If the instruction has live CPSR def, then it's not safe to fold it
H A DARMISelDAGToDAG.cpp138 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
/external/chromium_org/third_party/opus/src/celt/arm/
H A Darm2gnu.pl193 s/CPSR/cpsr/;
/external/libopus/celt/arm/
H A Darm2gnu.pl167 s/CPSR/cpsr/;
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1706 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
3938 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5401 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
7321 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7372 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7379 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7409 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7417 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7604 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7749 Inst.getOperand(4).getReg() == ARM::CPSR) ||
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
671 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp561 // implicitly set CPSR. Since it's not represented in the encoding, the
562 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
677 I->setReg(ARM::CPSR);
1112 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1119 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp874 O << "CPSR";
905 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
906 "Expect ARM CPSR register!");

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