Searched refs:CreateReg (Results 1 - 25 of 70) sorted by relevance

123

/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp183 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
251 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
276 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
359 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
362 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
365 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
393 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
426 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
471 baseReg = MCOperand::CreateReg(X8
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/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
597 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
600 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
645 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
649 MI.addOperand(MCOperand::CreateReg(getRe
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/external/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp42 NopInst.addOperand(MCOperand::CreateReg(0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
48 NopInst.addOperand(MCOperand::CreateReg(0));
49 NopInst.addOperand(MCOperand::CreateReg(0));
H A DThumb1InstrInfo.cpp30 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33 NopInst.addOperand(MCOperand::CreateReg(0));
H A DARMAsmPrinter.cpp1289 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1310 TmpInst.addOperand(MCOperand::CreateReg(0));
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1321 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1322 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1342 TmpInst.addOperand(MCOperand::CreateReg(0));
1344 TmpInst.addOperand(MCOperand::CreateReg(0));
1509 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1510 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1513 TmpInst.addOperand(MCOperand::CreateReg(
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H A DARMMCInstLower.cpp77 MCOp = MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp551 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
560 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
561 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
570 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
571 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
572 TmpInst.addOperand(MCOperand::CreateReg(RegNo));
593 Inst.addOperand(MCOperand::CreateReg(RegOrOffset));
594 Inst.addOperand(MCOperand::CreateReg(Mips::GP));
595 Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
599 Inst.addOperand(MCOperand::CreateReg(Mip
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H A DMipsNaClELFStreamer.cpp97 MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
98 MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
99 MaskInst.addOperand(MCOperand::CreateReg(MaskReg));
/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h33 Inst.addOperand(MCOperand::CreateReg(Reg));
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp382 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, function in class:__anon26038::MipsOperand
550 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
558 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
563 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
568 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
573 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
582 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
587 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
592 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
597 Inst.addOperand(MCOperand::CreateReg(getMSACtrlRe
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/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
81 MO.push_back(MachineOperand::CreateReg(0, false, false,
H A DX86MCInstLower.cpp359 MCOp = MCOperand::CreateReg(MO.getReg());
642 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
643 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
645 LEA.addOperand(MCOperand::CreateReg(0)); // index
647 LEA.addOperand(MCOperand::CreateReg(0)); // seg
650 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
651 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
653 LEA.addOperand(MCOperand::CreateReg(0)); // index
655 LEA.addOperand(MCOperand::CreateReg(0)); // seg
658 LEA.addOperand(MCOperand::CreateReg(X8
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/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp57 Inst.addOperand(MCOperand::CreateReg(RegNo));
194 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
204 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
215 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
217 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
227 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
229 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
239 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1707 Inst.addOperand(MCOperand::CreateReg(RegNum));
1737 Inst.addOperand(MCOperand::CreateReg(getReg()));
1742 Inst.addOperand(MCOperand::CreateReg(getReg()));
1749 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1750 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1759 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1777 Inst.addOperand(MCOperand::CreateReg(*I));
1978 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2005 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2068 Inst.addOperand(MCOperand::CreateReg(Memor
2529 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, function
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUMCInstLower.cpp51 MCOp = MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/R600/
H A DSIMachineFunctionInfo.cpp61 MBB.back().addOperand(*MF, MachineOperand::CreateReg(VGPR, false, true));
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUMCInstLower.cpp51 MCOp = MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h337 Inst.addOperand(MCOperand::CreateReg(getReg()));
368 Inst.addOperand(MCOperand::CreateReg(RegNo));
378 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
380 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
382 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
396 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
397 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
401 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
411 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
423 CreateReg(unsigne function in struct:llvm::X86Operand
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H A DX86AsmInstrumentation.cpp188 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
201 Inst.addOperand(MCOperand::CreateReg(X86::CL));
226 Inst.addOperand(MCOperand::CreateReg(X86::EDX));
269 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
328 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
364 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
375 Inst.addOperand(MCOperand::CreateReg(X86::AL));
400 Inst.addOperand(MCOperand::CreateReg(X86::ECX));
444 Inst.addOperand(MCOperand::CreateReg(X86::RAX));
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
277 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
284 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
289 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
305 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
307 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
310 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
321 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
/external/llvm/lib/Target/Sparc/
H A DSparcMCInstLower.cpp77 return MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp80 return MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp123 Inst.addOperand(MCOperand::CreateReg(Reg));
134 Inst.addOperand(MCOperand::CreateReg(Reg));
146 Inst.addOperand(MCOperand::CreateReg(Reg));
158 Inst.addOperand(MCOperand::CreateReg(Reg));
173 Inst.addOperand(MCOperand::CreateReg(Reg));
182 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
/external/llvm/lib/Target/Hexagon/
H A DHexagonMCInstLower.cpp58 MCO = MCOperand::CreateReg(MO.getReg());
/external/llvm/lib/Target/MSP430/
H A DMSP430MCInstLower.cpp127 MCOp = MCOperand::CreateReg(MO.getReg());

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