Searched refs:DAG (Results 1 - 25 of 128) sorted by relevance

123456

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
53 DebugLoc DL, SelectionDAG &DAG,
70 DebugLoc DL, SelectionDAG &DAG) const
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
88 // AMDIL DAG lowering
89 case ISD::SDIV: return LowerSDIV(Op, DAG);
90 case ISD::SREM: return LowerSREM(Op, DAG);
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
[all...]
H A DR600ISelLowering.h1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
10 // R600 DAG Lowering interface definition
29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
H A DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
33 /// of the DAG's MachineFunction. This returns a Register SDNode representing
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
47 DebugLoc DL, SelectionDAG &DAG,
54 DebugLoc DL, SelectionDAG &DAG) const;
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
70 const SelectionDAG &DAG,
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
53 DebugLoc DL, SelectionDAG &DAG,
70 DebugLoc DL, SelectionDAG &DAG) const
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
88 // AMDIL DAG lowering
89 case ISD::SDIV: return LowerSDIV(Op, DAG);
90 case ISD::SREM: return LowerSREM(Op, DAG);
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
[all...]
H A DR600ISelLowering.h1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
10 // R600 DAG Lowering interface definition
29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
H A DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
33 /// of the DAG's MachineFunction. This returns a Register SDNode representing
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
47 DebugLoc DL, SelectionDAG &DAG,
54 DebugLoc DL, SelectionDAG &DAG) const;
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
70 const SelectionDAG &DAG,
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp32 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, argument
48 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
49 DAG.getConstant(Size, PtrVT),
50 DAG.getConstant(Size / 256, PtrVT));
51 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
52 DAG.getConstant(Size, PtrVT));
56 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument
65 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
73 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument
80 return DAG
86 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dst, SDValue Byte, SDValue Size, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument
158 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
182 addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) argument
192 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
207 EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const argument
237 EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const argument
248 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
265 getBoundedStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Limit) argument
278 EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const argument
285 EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const argument
[all...]
H A DSystemZISelLowering.h1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
11 // selection DAG.
227 SelectionDAG &DAG) const override;
231 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
237 SDLoc DL, SelectionDAG &DAG,
245 SDLoc DL, SelectionDAG &DAG) const override;
247 SelectionDAG &DAG) const override;
254 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
255 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
256 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) cons
[all...]
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.h1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
11 /// \brief R600 DAG Lowering interface definition
29 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
33 SelectionDAG &DAG) const override;
39 SDLoc DL, SelectionDAG &DAG,
48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
54 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
56 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DAMDGPUISelLowering.h35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DSIISelLowering.h1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
11 /// \brief SI DAG Lowering interface definition
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
27 SelectionDAG &DAG) const;
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
35 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
37 bool fitsRegClass(SelectionDAG &DAG, cons
[all...]
H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
494 SDLoc DL, SelectionDAG &DAG) const {
495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
505 SelectionDAG &DAG = CLI.DAG; local
507 const Function &Fn = *DAG.getMachineFunction().getFunction();
517 DAG.getContext()->diagnose(NoCalls);
522 SelectionDAG &DAG) const {
529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1858 isU24(SDValue Op, SelectionDAG &DAG) argument
1866 isI24(SDValue Op, SelectionDAG &DAG) argument
1878 SelectionDAG &DAG = DCI.DAG; local
1890 constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width) argument
1933 SelectionDAG &DAG = DCI.DAG; local
2038 getOriginalFunctionArgs( SelectionDAG &DAG, const Function *F, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<ISD::InputArg> &OrigIns) const argument
2090 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
2165 computeKnownBitsForMinMax(const SDValue Op0, const SDValue Op1, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) argument
2180 computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
2246 ComputeNumSignBitsForTargetNode( SDValue Op, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp33 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, argument
40 const X86Subtarget &Subtarget = DAG.getTarget().getSubtarget<X86Subtarget>();
56 EVT IntPtr = DAG.getTargetLoweringInfo().getPointerTy();
57 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
66 TargetLowering::CallLoweringInfo CLI(DAG);
68 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
69 DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args),
73 std::pair<SDValue,SDValue> CallResult = DAG.getTargetLoweringInfo().LowerCallTo(CLI);
113 Count = DAG.getIntPtrConstant(SizeVal);
119 Count = DAG
176 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
206 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
209 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
210 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
211 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
212 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
213 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
214 case ISD::LOAD: return LowerLOAD(Op, DAG);
215 case ISD::STORE: return LowerSTORE(Op, DAG);
216 case ISD::VAARG: return LowerVAARG(Op, DAG);
415 isWordAligned(SDValue Value, SelectionDAG &DAG) argument
1034 SelectionDAG &DAG = CLI.DAG; local
1063 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
1110 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1248 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1272 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1609 SelectionDAG &DAG = DCI.DAG; local
1841 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
H A DXCoreISelLowering.h1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
113 SelectionDAG &DAG) const override;
116 // DAG node.
134 SDLoc dl, SelectionDAG &DAG,
142 SDLoc dl, SelectionDAG &DAG,
144 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
146 SelectionDAG &DAG) const;
149 SelectionDAG &DAG) cons
[all...]
H A DXCoreSelectionDAGInfo.cpp26 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, argument
35 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) {
36 const TargetLowering &TLI = *DAG.getTarget().getTargetLowering();
39 Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext());
44 TargetLowering::CallLoweringInfo CLI(DAG);
47 Type::getVoidTy(*DAG.getContext()),
48 DAG.getExternalSymbol("__memcpy_4", TLI.getPointerTy()),
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
11 // selection DAG.
76 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79 /// DAG node.
82 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) cons
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
11 // selection DAG.
210 APInt &KnownOne, const SelectionDAG &DAG,
228 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
263 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
342 SelectionDAG &DAG,
351 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
359 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
364 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
371 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLo
[all...]
H A DAArch64SelectionDAGInfo.cpp25 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src,
33 ? DAG.getTarget().getSubtarget<AArch64Subtarget>().getBZeroEntry()
40 DAG.getTarget().getTargetLowering());
43 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
51 TargetLowering::CallLoweringInfo CLI(DAG);
53 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
54 DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args), 0)
24 EmitTargetCodeForMemset( SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp28 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, argument
35 const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>();
67 Loads[i] = DAG.getLoad(VT, dl, Chain,
68 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
69 DAG.getConstant(SrcOff, MVT::i32)),
75 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
80 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
82 DAG.getConstant(DstOff, MVT::i32)),
87 Chain = DAG
148 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
230 SelectionDAG &DAG) const override;
233 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239 SelectionDAG &DAG) const override;
242 // DAG node.
261 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
268 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, argument
272 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, T
288 getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
302 getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp37 N->dump(&DAG);
45 N->dump(&DAG);
138 return DAG.getNode(N->getOpcode(), SDLoc(N),
146 return DAG.getNode(N->getOpcode(), SDLoc(N),
158 return DAG.getNode(ISD::BITCAST, SDLoc(N),
168 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 return DAG.getConvertRndSat(NewVT, SDLoc(N),
176 Op0, DAG.getValueType(NewVT),
177 DAG.getValueType(Op0.getValueType()),
184 return DAG
2638 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument
2691 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument
[all...]
H A DLegalizeDAG.cpp54 SelectionDAG &DAG; member in class:__anon25802::SelectionDAGLegalize
63 return TLI.getSetCCResultType(*DAG.getContext(), VT);
69 explicit SelectionDAGLegalize(SelectionDAG &DAG);
164 DAG.RemoveDeadNode(N);
170 DAG.ReplaceAllUsesWith(Old, New);
174 DAG.ReplaceAllUsesWith(Old, New);
178 DAG.ReplaceAllUsesWith(Old, New);
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
219 DAG(da
305 ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, const TargetLowering &TLI, SelectionDAGLegalize *DAGLegalize) argument
429 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, const TargetLowering &TLI, SDValue &ValResult, SDValue &ChainResult) argument
739 DAG, TLI, this); local
851 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
301 SelectionDAG &DAG);
306 SelectionDAG &DAG);
311 bool isUnary, SelectionDAG &DAG);
316 bool isUnary, SelectionDAG &DAG);
320 int isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG);
333 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
339 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
350 /// DAG nod
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
175 SDLoc DL, SelectionDAG &DAG) const {
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
194 DAG.getTarget(), RVLocs, *DAG
321 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
541 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
660 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS) argument
685 SelectionDAG &DAG = CLI.DAG; local
971 getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const argument
1711 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
1999 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument
2153 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2169 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2186 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2215 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2243 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2264 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2283 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2320 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2356 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2376 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
2399 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2423 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
2430 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2469 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2478 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
2514 LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) argument
2543 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument
2594 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument
2637 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument
2669 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2720 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2765 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument
[all...]

Completed in 5045 milliseconds

123456