Searched refs:Disp (Results 1 - 25 of 28) sorted by relevance

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/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp132 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
133 assert(isUInt<4>(Base) && isUInt<12>(Disp));
134 return (Base << 12) | Disp;
142 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
143 assert(isUInt<4>(Base) && isInt<20>(Disp));
144 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
154 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
155 return (Index << 16) | (Base << 12) | Disp;
163 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
175 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
[all...]
/external/llvm/lib/Target/MSP430/InstPrinter/
H A DMSP430InstPrinter.cpp64 const MCOperand &Disp = MI->getOperand(OpNo+1); local
77 if (Disp.isExpr())
78 O << *Disp.getExpr();
80 assert(Disp.isImm() && "Expected immediate in displacement field");
81 O << Disp.getImm();
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 int64_t Disp; member in struct:__anon26152::SystemZAddressingMode
64 : Form(form), DR(dr), Base(), Disp(0), Index(),
90 errs() << " Disp " << Disp;
155 SDValue &Base, SDValue &Disp) const;
157 SDValue &Base, SDValue &Disp, SDValue &Index) const;
161 // Base and Disp respectively.
163 SDValue &Base, SDValue &Disp) const;
167 // base and displacement in Base and Disp respectivel
210 selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
216 selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
222 selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
228 selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
234 selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
240 selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
246 selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
252 selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
476 shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) argument
600 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
634 selectBDXAddr(SystemZAddressingMode::AddrForm Form, SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
1135 SDValue Base, Disp, Index; local
[all...]
H A DSystemZISelLowering.cpp2670 int64_t Disp = MI->getOperand(2).getImm(); local
2676 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2685 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2709 // store %SrcReg, %Disp(%Index,%Base)
2713 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2743 int64_t Disp = MI->getOperand(2).getImm(); local
2759 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2760 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2778 // %OrigVal = L Disp(%Base)
2782 .addOperand(Base).addImm(Disp)
2866 int64_t Disp = MI->getOperand(2).getImm(); local
2977 int64_t Disp = MI->getOperand(2).getImm(); local
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp48 int16_t Disp; member in struct:__anon26028::MSP430ISelAddressMode
57 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
73 errs() << " Disp " << Disp << '\n';
124 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
150 AM.Disp += G->getOffset();
155 AM.Disp += CP->getOffset();
192 AM.Disp += Val;
235 AM.Disp += Offset;
250 SDValue &Base, SDValue &Disp) {
249 SelectAddr(SDValue N, SDValue &Base, SDValue &Disp) argument
[all...]
H A DMSP430AsmPrinter.cpp108 const MachineOperand &Disp = MI->getOperand(OpNum+1); local
113 if (Disp.isImm() && !Base.getReg())
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h35 /// with BP or SP and Disp being offsetted accordingly. The displacement may
50 int Disp; member in struct:llvm::X86AddressMode
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
79 MO.push_back(MachineOperand::CreateImm(Disp));
136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
138 MIB.addImm(AM.Disp);
H A DX86ISelDAGToDAG.cpp62 int32_t Disp; member in struct:__anon26191::X86ISelAddressMode
73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
118 dbgs() << " Disp " << Disp << '\n'
206 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 SDValue &Scale, SDValue &Index, SDValue &Disp,
213 SDValue &Scale, SDValue &Index, SDValue &Disp,
216 SDValue &Scale, SDValue &Index, SDValue &Disp,
220 SDValue &Index, SDValue &Disp,
226 SDValue &Index, SDValue &Disp,
237 getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1050 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val; local
1116 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue(); local
1310 SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1355 SelectScalarSSELoad(SDNode *Root, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment, SDValue &PatternNodeWithChain) argument
1422 SelectLEA64_32Addr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1461 SelectLEAAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1523 SelectTLSADDRAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1547 TryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2044 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32); local
2725 SDValue Base, Scale, Index, Disp, Segment; local
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H A DX86CodeEmitter.cpp89 intptr_t Disp = 0, intptr_t PCAdj = 0,
92 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
273 intptr_t Disp /* = 0 */,
276 intptr_t RelocCST = Disp;
290 MCE.emitDWordLE(Disp);
292 MCE.emitWordLE((int32_t)Disp);
322 intptr_t Disp /* = 0 */,
333 MCE.emitDWordLE(Disp);
335 MCE.emitWordLE((int32_t)Disp);
H A DX86FastISel.cpp626 // Now construct the final address. Note that the Disp, Scale,
711 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); local
713 if (isInt<32>(Disp)) {
714 AM.Disp = (uint32_t)Disp;
725 uint64_t Disp = (int32_t)AM.Disp; local
736 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
746 Disp
[all...]
/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp192 uint64_t Disp = Field & 0xfff;
195 Inst.addOperand(MCOperand::CreateImm(Disp));
202 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
205 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
213 uint64_t Disp = Field & 0xfff;
216 Inst.addOperand(MCOperand::CreateImm(Disp));
225 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
228 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
237 uint64_t Disp = Field & 0xfff;
240 Inst.addOperand(MCOperand::CreateImm(Disp));
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h197 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, argument
199 switch (Disp.getType()) {
203 return addImm(Disp.getImm() + off);
210 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
212 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
213 Disp.getTargetFlags());
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp662 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
680 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
943 const MCExpr *Disp = MCConstantExpr::Create(0, getContext()); local
944 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
951 const MCExpr *Disp = MCConstantExpr::Create(0, getContext()); local
952 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
979 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
986 if (isa<MCSymbolRefExpr>(Disp) && !Info.IsVarDecl) {
996 const MCBinaryExpr *BinOp = dyn_cast<MCBinaryExpr>(Disp);
998 isa<MCSymbolRefExpr>(BinOp ? BinOp->getLHS() : Disp);
978 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1214 const MCExpr *Disp = nullptr; local
1325 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext()); local
1404 const MCExpr *Disp = MCConstantExpr::Create(SM.getImm(), getContext()); local
1414 ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp) argument
1722 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext()); local
[all...]
H A DX86AsmInstrumentation.cpp202 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); local
204 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
228 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); local
230 X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
290 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); local
292 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
330 const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx); local
332 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
376 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); local
378 X86Operand::CreateMem(0, Disp, X8
402 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); local
463 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); local
[all...]
H A DX86Operand.h51 const MCExpr *Disp; member in struct:llvm::X86Operand::MemOp
105 return Mem.Disp;
444 CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, argument
448 Res->Mem.Disp = Disp;
461 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, argument
474 Res->Mem.Disp = Disp;
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); local
65 Disp.isImm() && Disp.getImm() < 0x10000)
122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
391 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); local
421 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
465 if (Disp.isImm() && isDisp8(Disp.getImm())) {
466 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
473 EmitImmediate(Disp, M
[all...]
/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.cpp21 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, argument
23 O << Disp; local
148 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
150 O << Disp << '(' << Length;
H A DSystemZInstPrinter.h34 static void printAddress(unsigned Base, int64_t Disp, unsigned Index,
/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp86 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
95 const MCExpr *Disp; member in struct:__anon26144::SystemZOperand::MemOp
152 createMem(RegisterKind RegKind, unsigned Base, const MCExpr *Disp, argument
159 Op->Mem.Disp = Disp;
214 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
217 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
247 addExpr(Inst, Mem.Disp);
253 addExpr(Inst, Mem.Disp);
260 addExpr(Inst, Mem.Disp);
495 parseAddress(unsigned &Base, const MCExpr *&Disp, unsigned &Index, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) argument
549 const MCExpr *Disp; local
[all...]
/external/llvm/tools/llvm-objdump/
H A DCOFFDump.cpp225 uint64_t Offset, uint32_t Disp) {
229 if (Disp > 0)
230 Out << format(" + 0x%04x", Disp);
232 Out << format("0x%04x", Disp);
223 printCOFFSymbolAddress(llvm::raw_ostream &Out, const std::vector<RelocationRef> &Rels, uint64_t Offset, uint32_t Disp) argument
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp264 uint64_t Disp = Imm & 0xFFFF;
288 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
299 uint64_t Disp = Imm & 0x3FFF;
309 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
/external/llvm/lib/Target/Mips/
H A DMipsConstantIslandPass.cpp389 unsigned Disp, bool NegativeOK);
408 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
412 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
/external/llvm/lib/Target/AArch64/
H A DAArch64BranchRelaxation.cpp86 bool isBlockInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
/external/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp295 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
299 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
319 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp125 bool SelectAddrImm(SDValue N, SDValue &Disp, argument
127 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
159 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { argument
160 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);

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