/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
H A D | programopt.c | 91 newInst[i].DstReg.File = PROGRAM_OUTPUT; 92 newInst[i].DstReg.Index = VERT_RESULT_HPOS; 93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); 163 newInst[0].DstReg.File = PROGRAM_TEMPORARY; 164 newInst[0].DstReg.Index = hposTemp; 165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; 175 newInst[i].DstReg.File = PROGRAM_TEMPORARY; 176 newInst[i].DstReg.Index = hposTemp; 177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; 190 newInst[3].DstReg [all...] |
H A D | prog_optimize.c | 88 channel_mask = inst->DstReg.WriteMask & dst_mask; 134 const GLuint mask = mov->DstReg.WriteMask; 234 if (inst->DstReg.File == file) { 235 const GLuint index = inst->DstReg.Index; 237 inst->DstReg.Index = map[index]; 298 if (inst->DstReg.File == PROGRAM_TEMPORARY) { 299 const GLuint index = inst->DstReg.Index; 302 if (inst->DstReg.RelAddr) { 326 if (numDst != 0 && inst->DstReg.File == PROGRAM_TEMPORARY) { 327 GLint chan, index = inst->DstReg [all...] |
H A D | prog_instruction.c | 53 inst[i].DstReg.File = PROGRAM_UNDEFINED; 54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; 55 inst[i].DstReg.CondMask = COND_TR; 56 inst[i].DstReg.CondSwizzle = SWIZZLE_NOOP; 307 if (inst->DstReg.WriteMask == WRITEMASK_X || 308 inst->DstReg.WriteMask == WRITEMASK_Y || 309 inst->DstReg.WriteMask == WRITEMASK_Z || 310 inst->DstReg.WriteMask == WRITEMASK_W || 311 inst->DstReg.WriteMask == 0x0) { 318 if (inst->SrcReg[i].File == inst->DstReg [all...] |
/external/mesa3d/src/mesa/program/ |
H A D | programopt.c | 91 newInst[i].DstReg.File = PROGRAM_OUTPUT; 92 newInst[i].DstReg.Index = VERT_RESULT_HPOS; 93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); 163 newInst[0].DstReg.File = PROGRAM_TEMPORARY; 164 newInst[0].DstReg.Index = hposTemp; 165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; 175 newInst[i].DstReg.File = PROGRAM_TEMPORARY; 176 newInst[i].DstReg.Index = hposTemp; 177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; 190 newInst[3].DstReg [all...] |
H A D | prog_optimize.c | 88 channel_mask = inst->DstReg.WriteMask & dst_mask; 134 const GLuint mask = mov->DstReg.WriteMask; 234 if (inst->DstReg.File == file) { 235 const GLuint index = inst->DstReg.Index; 237 inst->DstReg.Index = map[index]; 298 if (inst->DstReg.File == PROGRAM_TEMPORARY) { 299 const GLuint index = inst->DstReg.Index; 302 if (inst->DstReg.RelAddr) { 326 if (numDst != 0 && inst->DstReg.File == PROGRAM_TEMPORARY) { 327 GLint chan, index = inst->DstReg [all...] |
H A D | prog_instruction.c | 53 inst[i].DstReg.File = PROGRAM_UNDEFINED; 54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; 55 inst[i].DstReg.CondMask = COND_TR; 56 inst[i].DstReg.CondSwizzle = SWIZZLE_NOOP; 307 if (inst->DstReg.WriteMask == WRITEMASK_X || 308 inst->DstReg.WriteMask == WRITEMASK_Y || 309 inst->DstReg.WriteMask == WRITEMASK_Z || 310 inst->DstReg.WriteMask == WRITEMASK_W || 311 inst->DstReg.WriteMask == 0x0) { 318 if (inst->SrcReg[i].File == inst->DstReg [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_program_tex.c | 68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 69 inst_mov->U.I.DstReg.Index = temp; 90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; 91 inst_rcp->U.I.DstReg.Index = temp; 92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; 101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; 102 inst_mul->U.I.DstReg.Index = temp; 165 struct rc_dst_register output_reg = inst->U.I.DstReg; 171 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 172 inst->U.I.DstReg [all...] |
H A D | r3xx_vertprog.c | 194 t_dst_index(vp, &vpi->DstReg), 195 t_dst_mask(vpi->DstReg.WriteMask), 196 t_dst_class(vpi->DstReg.File)); 210 t_dst_index(vp, &vpi->DstReg), 211 t_dst_mask(vpi->DstReg.WriteMask), 212 t_dst_class(vpi->DstReg.File)); 226 t_dst_index(vp, &vpi->DstReg), 227 t_dst_mask(vpi->DstReg.WriteMask), 228 t_dst_class(vpi->DstReg.File)); 243 t_dst_index(vp, &vpi->DstReg), [all...] |
H A D | radeon_compiler.c | 128 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) 129 c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index; 180 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { 181 inst->U.I.DstReg.Index = new_output; 182 inst->U.I.DstReg.WriteMask &= writemask; 203 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { 204 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 205 inst->U.I.DstReg [all...] |
H A D | radeon_pair_translate.c | 90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; 91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; 275 inst->DstReg.WriteMask); 284 if (inst->DstReg.File == RC_FILE_OUTPUT) { 285 if (inst->DstReg.Index == c->OutputDepth) { 286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); 289 if (inst->DstReg.Index == c->OutputColor[i]) { 293 inst->DstReg.WriteMask & RC_MASK_XYZ; 295 GET_BIT(inst->DstReg.WriteMask, 3); 302 pair->RGB.DestIndex = inst->DstReg [all...] |
H A D | radeon_program_alu.c | 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg) 54 fpi->U.I.DstReg = DstReg; 62 struct rc_dst_register DstReg, 72 fpi->U.I.DstReg = DstReg; 81 struct rc_dst_register DstReg, 92 fpi->U.I.DstReg = DstReg; 204 if (inst->U.I.DstReg 42 emit1( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg) argument 59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument 78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_program_tex.c | 68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 69 inst_mov->U.I.DstReg.Index = temp; 90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; 91 inst_rcp->U.I.DstReg.Index = temp; 92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; 101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; 102 inst_mul->U.I.DstReg.Index = temp; 165 struct rc_dst_register output_reg = inst->U.I.DstReg; 171 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 172 inst->U.I.DstReg [all...] |
H A D | r3xx_vertprog.c | 194 t_dst_index(vp, &vpi->DstReg), 195 t_dst_mask(vpi->DstReg.WriteMask), 196 t_dst_class(vpi->DstReg.File)); 210 t_dst_index(vp, &vpi->DstReg), 211 t_dst_mask(vpi->DstReg.WriteMask), 212 t_dst_class(vpi->DstReg.File)); 226 t_dst_index(vp, &vpi->DstReg), 227 t_dst_mask(vpi->DstReg.WriteMask), 228 t_dst_class(vpi->DstReg.File)); 243 t_dst_index(vp, &vpi->DstReg), [all...] |
H A D | radeon_compiler.c | 128 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) 129 c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index; 180 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { 181 inst->U.I.DstReg.Index = new_output; 182 inst->U.I.DstReg.WriteMask &= writemask; 203 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { 204 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 205 inst->U.I.DstReg [all...] |
H A D | radeon_pair_translate.c | 90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; 91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; 275 inst->DstReg.WriteMask); 284 if (inst->DstReg.File == RC_FILE_OUTPUT) { 285 if (inst->DstReg.Index == c->OutputDepth) { 286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); 289 if (inst->DstReg.Index == c->OutputColor[i]) { 293 inst->DstReg.WriteMask & RC_MASK_XYZ; 295 GET_BIT(inst->DstReg.WriteMask, 3); 302 pair->RGB.DestIndex = inst->DstReg [all...] |
H A D | radeon_program_alu.c | 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg) 54 fpi->U.I.DstReg = DstReg; 62 struct rc_dst_register DstReg, 72 fpi->U.I.DstReg = DstReg; 81 struct rc_dst_register DstReg, 92 fpi->U.I.DstReg = DstReg; 204 if (inst->U.I.DstReg 42 emit1( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg) argument 59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument 78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 31 /// DstReg - The register that will be left after coalescing. It can be a 33 unsigned DstReg; member in class:llvm::CoalescerPair 38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 56 /// NewRC - The register class of the coalesced register, or NULL if DstReg 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 78 /// because DstReg i [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 96 unsigned DstReg = MI.getOperand(0).getReg(); local 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); 124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0); 125 unsigned DstBase = TRI.getHWRegIndex(DstReg); 126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
H A D | SIInstrInfo.h | 45 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 96 unsigned DstReg = MI.getOperand(0).getReg(); local 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); 124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0); 125 unsigned DstBase = TRI.getHWRegIndex(DstReg); 126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
H A D | SIInstrInfo.h | 45 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
|
/external/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 125 unsigned DstReg; local 128 DstReg = MI.getOperand(Chan).getReg(); 130 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; 133 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 154 unsigned DstReg; local 157 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; 159 DstReg = MI.getOperand(Chan-2).getReg(); 162 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 182 unsigned DstReg = MI.getOperand(0).getReg(); local 186 TRI.getSubReg(DstReg, TR 201 unsigned DstReg = MI.getOperand(0).getReg(); local 271 unsigned DstReg = MI.getOperand( local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
H A D | st_atom_pixeltransfer.c | 163 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 164 inst[ic].DstReg.Index = colorTemp; 187 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 188 inst[ic].DstReg.Index = colorTemp; 216 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 217 inst[ic].DstReg.Index = temp; 218 inst[ic].DstReg.WriteMask = WRITEMASK_XY; /* write R,G */ 228 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 229 inst[ic].DstReg.Index = temp; 230 inst[ic].DstReg [all...] |
/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_atom_pixeltransfer.c | 163 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 164 inst[ic].DstReg.Index = colorTemp; 187 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 188 inst[ic].DstReg.Index = colorTemp; 216 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 217 inst[ic].DstReg.Index = temp; 218 inst[ic].DstReg.WriteMask = WRITEMASK_XY; /* write R,G */ 228 inst[ic].DstReg.File = PROGRAM_TEMPORARY; 229 inst[ic].DstReg.Index = temp; 230 inst[ic].DstReg [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 142 unsigned DstReg = Dst.getReg(); local 145 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 150 PeepholeMap[DstReg] = SrcReg; 164 unsigned DstReg = Dst.getReg(); local 166 PeepholeMap[DstReg] = SrcReg; 181 unsigned DstReg = Dst.getReg(); local 183 PeepholeDoubleRegsMap[DstReg] = 193 unsigned DstReg = Dst.getReg(); local 196 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 201 PeepholeMap[DstReg] 216 unsigned DstReg = Dst.getReg(); local [all...] |