Searched refs:FRT (Results 1 - 3 of 3) sorted by relevance

/external/qemu/disas/
H A Dppc.c617 /* The FRS field in an X form instruction or the FRT field in a D, X
620 #define FRT FRS
4081 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4083 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4085 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4383 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4401 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4407 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4409 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4422 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA
616 #define FRT macro
[all...]
/external/valgrind/main/memcheck/tests/ppc32/
H A Dpower_ISA2_05.c58 printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
136 /* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
153 double FRT, FRA, FRB; local
160 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
162 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
/external/valgrind/main/memcheck/tests/ppc64/
H A Dpower_ISA2_05.c56 printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
135 /* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
152 double FRT, FRA, FRB; local
159 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
161 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);

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