/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 29 SmallVectorImpl<MCFixup> &Fixups) const; 32 SmallVectorImpl<MCFixup> &Fixups) const { 37 SmallVectorImpl<MCFixup> &Fixups) const { 41 SmallVectorImpl<MCFixup> &Fixups) const { 48 SmallVectorImpl<MCFixup> &Fixups) const { 52 SmallVectorImpl<MCFixup> &Fixups) const {
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H A D | R600MCCodeEmitter.cpp | 54 SmallVectorImpl<MCFixup> &Fixups) const; 58 SmallVectorImpl<MCFixup> &Fixups) const; 61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 66 SmallVectorImpl<MCFixup> &Fixups, 68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 151 SmallVectorImpl<MCFixup> &Fixups) const { 153 EmitTexInstr(MI, Fixups, OS); 164 uint64_t inst = getBinaryCodeForInstr(MI, Fixups); 176 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups); 186 EmitALUInstr(MI, Fixups, O 192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument [all...] |
H A D | SIMCCodeEmitter.cpp | 75 SmallVectorImpl<MCFixup> &Fixups) const; 79 SmallVectorImpl<MCFixup> &Fixups) const; 132 SmallVectorImpl<MCFixup> &Fixups) const { 133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups); 142 SmallVectorImpl<MCFixup> &Fixups) const {
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 29 SmallVectorImpl<MCFixup> &Fixups) const; 32 SmallVectorImpl<MCFixup> &Fixups) const { 37 SmallVectorImpl<MCFixup> &Fixups) const { 41 SmallVectorImpl<MCFixup> &Fixups) const { 48 SmallVectorImpl<MCFixup> &Fixups) const { 52 SmallVectorImpl<MCFixup> &Fixups) const {
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H A D | R600MCCodeEmitter.cpp | 54 SmallVectorImpl<MCFixup> &Fixups) const; 58 SmallVectorImpl<MCFixup> &Fixups) const; 61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 66 SmallVectorImpl<MCFixup> &Fixups, 68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 151 SmallVectorImpl<MCFixup> &Fixups) const { 153 EmitTexInstr(MI, Fixups, OS); 164 uint64_t inst = getBinaryCodeForInstr(MI, Fixups); 176 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups); 186 EmitALUInstr(MI, Fixups, O 192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument [all...] |
H A D | SIMCCodeEmitter.cpp | 75 SmallVectorImpl<MCFixup> &Fixups) const; 79 SmallVectorImpl<MCFixup> &Fixups) const; 132 SmallVectorImpl<MCFixup> &Fixups) const { 133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups); 142 SmallVectorImpl<MCFixup> &Fixups) const {
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 39 SmallVectorImpl<MCFixup> &Fixups, 45 SmallVectorImpl<MCFixup> &Fixups, 49 // MO in MI. Fixups is the list of fixups against MI. 51 SmallVectorImpl<MCFixup> &Fixups, 59 SmallVectorImpl<MCFixup> &Fixups, 62 SmallVectorImpl<MCFixup> &Fixups, 65 SmallVectorImpl<MCFixup> &Fixups, 68 SmallVectorImpl<MCFixup> &Fixups, 71 SmallVectorImpl<MCFixup> &Fixups, 75 // Offset bytes from the start of MI. Add the fixup to Fixups 82 getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 87 getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 103 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 117 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 128 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 138 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 148 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 159 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 171 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 182 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset) const argument [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.h | 54 SmallVectorImpl<MCFixup> &Fixups, 60 SmallVectorImpl<MCFixup> &Fixups, 67 SmallVectorImpl<MCFixup> &Fixups, 74 SmallVectorImpl<MCFixup> &Fixups, 81 SmallVectorImpl<MCFixup> &Fixups, 88 SmallVectorImpl<MCFixup> &Fixups, 95 SmallVectorImpl<MCFixup> &Fixups, 102 SmallVectorImpl<MCFixup> &Fixups, 109 SmallVectorImpl<MCFixup> &Fixups, 115 SmallVectorImpl<MCFixup> &Fixups, [all...] |
H A D | MipsMCCodeEmitter.cpp | 146 SmallVectorImpl<MCFixup> &Fixups, 169 unsigned long N = Fixups.size(); 170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 182 if (Fixups.size() > N) 183 Fixups.pop_back(); 186 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 205 SmallVectorImpl<MCFixup> &Fixups, 217 Fixups.push_back(MCFixup::Create(0, Expr, 227 SmallVectorImpl<MCFixup> &Fixups, 239 Fixups [all...] |
H A D | MipsFixupKinds.h | 25 enum Fixups { enum in namespace:llvm::Mips
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 49 SmallVectorImpl<MCFixup> &Fixups, 52 SmallVectorImpl<MCFixup> &Fixups, 55 SmallVectorImpl<MCFixup> &Fixups, 58 SmallVectorImpl<MCFixup> &Fixups, 61 SmallVectorImpl<MCFixup> &Fixups, 64 SmallVectorImpl<MCFixup> &Fixups, 67 SmallVectorImpl<MCFixup> &Fixups, 70 SmallVectorImpl<MCFixup> &Fixups, 73 SmallVectorImpl<MCFixup> &Fixups, 76 SmallVectorImpl<MCFixup> &Fixups, 163 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 175 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 188 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 201 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 213 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 225 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 244 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 263 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 279 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 292 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 304 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
H A D | PPCFixupKinds.h | 19 enum Fixups { enum in namespace:llvm::PPC
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 44 SmallVectorImpl<MCFixup> &Fixups, 50 SmallVectorImpl<MCFixup> &Fixups, 56 SmallVectorImpl<MCFixup> &Fixups, 60 SmallVectorImpl<MCFixup> &Fixups, 63 SmallVectorImpl<MCFixup> &Fixups, 66 SmallVectorImpl<MCFixup> &Fixups, 69 SmallVectorImpl<MCFixup> &Fixups, 84 SmallVectorImpl<MCFixup> &Fixups, 86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 104 uint64_t op = getMachineOpValue(MI, MO, Fixups, ST 83 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 114 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 141 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 176 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 189 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 201 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
H A D | SparcFixupKinds.h | 17 enum Fixups { enum in namespace:llvm::Sparc
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H A D | SparcMCExpr.h | 85 Sparc::Fixups getFixupKind() const { return getFixupKind(Kind); } 106 static Sparc::Fixups getFixupKind(VariantKind Kind);
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86FixupKinds.h | 17 enum Fixups { enum in namespace:llvm::X86
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 50 SmallVectorImpl<MCFixup> &Fixups, 56 SmallVectorImpl<MCFixup> &Fixups, 64 SmallVectorImpl<MCFixup> &Fixups, 70 SmallVectorImpl<MCFixup> &Fixups, 76 SmallVectorImpl<MCFixup> &Fixups, 82 SmallVectorImpl<MCFixup> &Fixups, 88 SmallVectorImpl<MCFixup> &Fixups, 95 SmallVectorImpl<MCFixup> &Fixups, 101 SmallVectorImpl<MCFixup> &Fixups, 107 SmallVectorImpl<MCFixup> &Fixups, 216 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 227 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 248 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 274 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 301 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 323 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 343 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 352 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 371 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 393 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 421 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 445 getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 453 getSIMDShift64_32OpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 462 getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 471 getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 481 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 490 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 499 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 508 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 517 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 526 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 535 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 544 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 553 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 563 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 605 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
H A D | AArch64FixupKinds.h | 18 enum Fixups { enum in namespace:llvm::AArch64
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 32 SmallVectorImpl<MCFixup> &Fixups, 36 SmallVectorImpl<MCFixup> &Fixups, 35 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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H A D | SIMCCodeEmitter.cpp | 58 SmallVectorImpl<MCFixup> &Fixups, 63 SmallVectorImpl<MCFixup> &Fixups, 130 SmallVectorImpl<MCFixup> &Fixups, 133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI); 174 SmallVectorImpl<MCFixup> &Fixups, 182 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 129 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 172 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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H A D | R600MCCodeEmitter.cpp | 45 SmallVectorImpl<MCFixup> &Fixups, 50 SmallVectorImpl<MCFixup> &Fixups, 90 SmallVectorImpl<MCFixup> &Fixups, 100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); 124 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); 134 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); 89 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 69 SmallVectorImpl<MCFixup> &Fixups, 75 SmallVectorImpl<MCFixup> &Fixups, 82 SmallVectorImpl<MCFixup> &Fixups, 87 SmallVectorImpl<MCFixup> &Fixups, 93 SmallVectorImpl<MCFixup> &Fixups, 99 SmallVectorImpl<MCFixup> &Fixups, 104 SmallVectorImpl<MCFixup> &Fixups, 109 SmallVectorImpl<MCFixup> &Fixups, 114 SmallVectorImpl<MCFixup> &Fixups, 120 SmallVectorImpl<MCFixup> &Fixups, 191 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 264 getCCOutOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 273 getSOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 308 getT2SOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 341 getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 509 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument 605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 998 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1054 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1088 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1103 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1126 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1138 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1158 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1195 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1211 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1226 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1237 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1276 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1324 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
H A D | ARMFixupKinds.h | 17 enum Fixups { enum in namespace:llvm::ARM
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/external/llvm/include/llvm/MC/ |
H A D | MCCodeEmitter.h | 39 SmallVectorImpl<MCFixup> &Fixups,
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/external/llvm/lib/MC/ |
H A D | WinCOFFStreamer.cpp | 49 SmallVector<MCFixup, 4> Fixups; local 52 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI); 56 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) { 57 Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size()); 58 DF->getFixups().push_back(Fixups[i]);
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