Searched refs:GPRArgRegs (Results 1 - 4 of 4) sorted by relevance
/external/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.h | 77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; local 83 Reg = State.AllocateReg(GPRArgRegs, 4);
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H A D | ARMISelLowering.cpp | 85 static const MCPhysReg GPRArgRegs[] = { variable 1792 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1802 reg = State->AllocateReg(GPRArgRegs, 4); 1813 while (State->AllocateReg(GPRArgRegs, 4)) 1830 State->AllocateReg(GPRArgRegs, 4); 2736 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2737 sizeof(GPRArgRegs) / 2738 sizeof(GPRArgRegs[0])); 2810 (GPRArgRegs, array_lengthof(GPRArgRegs)); [all...] |
H A D | ARMFastISel.cpp | 3036 static const uint16_t GPRArgRegs[] = { local 3044 unsigned SrcReg = GPRArgRegs[Idx];
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1847 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2, local 1850 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs); 1852 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs); 1862 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
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