Searched refs:Imm (Results 1 - 25 of 144) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { argument
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) { argument
86 return Imm & 0x3f;
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f);
118 static inline unsigned getArithShiftValue(unsigned Imm) { argument
119 return Imm
98 getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm) argument
123 getExtendType(unsigned Imm) argument
138 getArithExtendType(unsigned Imm) argument
170 getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm) argument
178 getMemDoShift(unsigned Imm) argument
184 getMemExtendType(unsigned Imm) argument
346 getFPImmFloat(unsigned Imm) argument
374 getFP32Imm(const APInt &Imm) argument
402 getFP64Imm(const APInt &Imm) argument
432 isAdvSIMDModImmType1(uint64_t Imm) argument
437 encodeAdvSIMDModImmType1(uint64_t Imm) argument
441 decodeAdvSIMDModImmType1(uint8_t Imm) argument
447 isAdvSIMDModImmType2(uint64_t Imm) argument
452 encodeAdvSIMDModImmType2(uint64_t Imm) argument
456 decodeAdvSIMDModImmType2(uint8_t Imm) argument
462 isAdvSIMDModImmType3(uint64_t Imm) argument
467 encodeAdvSIMDModImmType3(uint64_t Imm) argument
471 decodeAdvSIMDModImmType3(uint8_t Imm) argument
477 isAdvSIMDModImmType4(uint64_t Imm) argument
482 encodeAdvSIMDModImmType4(uint64_t Imm) argument
486 decodeAdvSIMDModImmType4(uint8_t Imm) argument
492 isAdvSIMDModImmType5(uint64_t Imm) argument
498 encodeAdvSIMDModImmType5(uint64_t Imm) argument
502 decodeAdvSIMDModImmType5(uint8_t Imm) argument
508 isAdvSIMDModImmType6(uint64_t Imm) argument
514 encodeAdvSIMDModImmType6(uint64_t Imm) argument
518 decodeAdvSIMDModImmType6(uint8_t Imm) argument
524 isAdvSIMDModImmType7(uint64_t Imm) argument
529 encodeAdvSIMDModImmType7(uint64_t Imm) argument
533 decodeAdvSIMDModImmType7(uint8_t Imm) argument
539 isAdvSIMDModImmType8(uint64_t Imm) argument
544 decodeAdvSIMDModImmType8(uint8_t Imm) argument
549 encodeAdvSIMDModImmType8(uint64_t Imm) argument
554 isAdvSIMDModImmType9(uint64_t Imm) argument
560 encodeAdvSIMDModImmType9(uint64_t Imm) argument
564 decodeAdvSIMDModImmType9(uint8_t Imm) argument
574 isAdvSIMDModImmType10(uint64_t Imm) argument
594 encodeAdvSIMDModImmType10(uint64_t Imm) argument
622 decodeAdvSIMDModImmType10(uint8_t Imm) argument
636 isAdvSIMDModImmType11(uint64_t Imm) argument
643 encodeAdvSIMDModImmType11(uint64_t Imm) argument
671 decodeAdvSIMDModImmType11(uint8_t Imm) argument
686 isAdvSIMDModImmType12(uint64_t Imm) argument
692 encodeAdvSIMDModImmType12(uint64_t Imm) argument
720 decodeAdvSIMDModImmType12(uint8_t Imm) argument
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/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
39 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
41 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
43 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
50 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
63 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
68 void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
H A DX86ShuffleDecode.cpp24 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument
32 unsigned ZMask = Imm & 15;
33 unsigned CountD = (Imm >> 4) & 3;
34 unsigned CountS = (Imm >> 6) & 3;
65 void DecodePALIGNRMask(MVT VT, unsigned Imm, argument
68 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
86 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument
92 unsigned NewImm = Imm;
98 if (NumLaneElts == 4) NewImm = Imm; // reload imm
102 void DecodePSHUFHWMask(MVT VT, unsigned Imm, argument
118 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
137 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
196 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
212 DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF;
129 static inline unsigned getSOImmValRot(unsigned Imm) {
130 return (Imm >> 8) * 2;
133 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
137 static inline unsigned getSOImmValRotate(unsigned Imm) { argument
140 if ((Imm & ~255U) == 0) return 0;
143 unsigned TZ = countTrailingZeros(Imm);
218 getThumbImmValShift(unsigned Imm) argument
237 getThumbImm16ValShift(unsigned Imm) argument
271 unsigned u, Vs, Imm; local
335 isT2SOImmTwoPartVal(unsigned Imm) argument
362 getT2SOImmTwoPartFirst(unsigned Imm) argument
379 getT2SOImmTwoPartSecond(unsigned Imm) argument
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/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument
125 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument
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H A DMipsISelDAGToDAG.h84 virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
86 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
88 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
90 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
92 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
94 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
96 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
98 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
100 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
102 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
118 getImm(const SDNode *Node, uint64_t Imm) argument
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H A DMipsAnalyzeImmediate.h25 /// Analyze - Get an instruction sequence to load immediate Imm. The last
28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
36 /// load immediate Imm
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
40 /// load immediate Imm
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
44 /// load immediate Imm
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
47 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
48 void GetInstSeqLs(uint64_t Imm, unsigne
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H A DMipsSEISelDAGToDAG.h72 bool selectVSplat(SDNode *N, APInt &Imm) const override;
74 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
77 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
79 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
81 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
83 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
85 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
87 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
89 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
91 bool selectVSplatSimm5(SDValue N, SDValue &Imm) cons
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H A DMipsISelDAGToDAG.cpp110 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
115 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
120 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
125 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
130 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
135 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
140 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
145 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
150 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
155 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
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H A DMipsFastISel.cpp86 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
323 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); local
327 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
333 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
362 int64_t Imm; local
364 Imm = CI->getSExtValue();
366 Imm = CI->getZExtValue();
367 return Materialize32BitInt(Imm, RC);
370 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm, argument
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H A DMipsSEISelDAGToDAG.cpp407 // Returns true and sets Imm if:
410 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
428 Imm = SplatValue;
436 // true and sets Imm if:
450 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, argument
462 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
472 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
473 return selectVSplatCommon(N, Imm, false, 1);
477 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
478 return selectVSplatCommon(N, Imm, fals
690 int64_t Imm = CN->getSExtValue(); local
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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp88 IntFloatUnion Imm; local
90 Imm.I = MO.getImm();
92 Imm.F = MO.getFPImm();
96 if (Imm.I >= 0 && Imm.I <= 64)
97 return 128 + Imm.I;
99 if (Imm.I >= -16 && Imm.I <= -1)
100 return 192 + abs(Imm.I);
102 if (Imm
157 IntFloatUnion Imm; local
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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp19 int64_t Imm = Inst.getOperand(0).getImm();
20 Target = Addr+Size+Imm;
/external/llvm/test/MC/Mips/
H A Dsym-expr.s11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp75 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
77 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
79 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
138 unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument
140 return TargetTransformInfo::getIntImmCost(Imm, Ty);
148 if (Imm == 0)
151 if (Imm.getBitWidth() <= 64) {
152 if (isInt<16>(Imm.getSExtValue()))
155 if (isInt<32>(Imm.getSExtValue())) {
157 if ((Imm
167 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument
191 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument
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H A DPPCISelDAGToDAG.cpp82 inline SDValue getI32Imm(unsigned Imm) { argument
83 return CurDAG->getTargetConstant(Imm, MVT::i32);
88 inline SDValue getI64Imm(uint64_t Imm) { argument
89 return CurDAG->getTargetConstant(Imm, MVT::i64);
93 inline SDValue getSmallIPtrImm(unsigned Imm) { argument
94 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
295 static bool isIntS16Immediate(SDNode *N, short &Imm) { argument
299 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
301 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
303 return Imm
306 isIntS16Immediate(SDValue Op, short &Imm) argument
313 isInt32Immediate(SDNode *N, unsigned &Imm) argument
323 isInt64Immediate(SDNode *N, uint64_t &Imm) argument
333 isInt32Immediate(SDValue N, unsigned &Imm) argument
341 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
498 unsigned Imm; local
539 uint64_t Imm; local
746 unsigned Imm; local
933 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); local
1037 unsigned Imm; local
1147 unsigned Imm, Imm2, SH, MB, ME; local
1220 unsigned Imm, SH, MB, ME; local
1232 unsigned Imm, SH, MB, ME; local
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/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp110 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
111 assert(isUInt<N>(Imm) && "Invalid immediate");
112 Inst.addOperand(MCOperand::CreateImm(Imm));
117 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
118 assert(isUInt<N>(Imm) && "Invalid immediate");
119 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
123 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm,
126 return decodeUImmOperand<4>(Inst, Imm);
129 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
131 return decodeUImmOperand<4>(Inst, Imm);
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/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp99 int64_t Imm = MO.getImm(); local
103 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
107 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
111 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
149 int64_t Imm = MO.getImm(); local
153 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
156 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
223 int Imm = (int) MO.getImm(); local
225 if (Imm)
228 switch (Imm) {
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/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) { argument
114 int32_t SImm = static_cast<int32_t>(Imm);
120 if (Imm == FloatToBits(1.0f) ||
121 Imm == FloatToBits(-1.0f) ||
122 Imm == FloatToBits(0.5f) ||
123 Imm == FloatToBits(-0.5f) ||
124 Imm == FloatToBits(2.0f) ||
125 Imm == FloatToBits(-2.0f) ||
126 Imm == FloatToBits(4.0f) ||
127 Imm
175 unsigned Imm = MI->getOperand(OpNum).getImm(); local
219 int32_t Imm = MI->getOperand(OpNo).getImm(); local
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.h46 int64_t Imm) const;
H A DSIInstrInfo.cpp53 int64_t Imm) const
57 MachineInstrBuilder(MI).addImm(Imm);
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.h46 int64_t Imm) const;
H A DSIInstrInfo.cpp53 int64_t Imm) const
57 MachineInstrBuilder(MI).addImm(Imm);
/external/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h254 virtual bool isLegalAddImmediate(int64_t Imm) const;
260 virtual bool isLegalICmpImmediate(int64_t Imm) const;
307 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
312 virtual unsigned getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
315 const APInt &Imm, Type *Ty) const;
/external/llvm/include/llvm/CodeGen/
H A DFastISel.h210 uint64_t Imm);
229 uint64_t Imm);
239 uint64_t Imm, MVT ImmType);
246 uint64_t Imm);
287 uint64_t Imm);
308 uint64_t Imm);
322 uint64_t Imm);

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