Searched refs:Inst (Results 1 - 25 of 251) sorted by relevance

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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
/external/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h34 virtual bool isBranch(const MCInst &Inst) const {
35 return Info->get(Inst.getOpcode()).isBranch();
38 virtual bool isConditionalBranch(const MCInst &Inst) const {
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
42 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
46 virtual bool isIndirectBranch(const MCInst &Inst) const {
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
50 virtual bool isCall(const MCInst &Inst) const {
51 return Info->get(Inst
[all...]
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
62 return Inst;
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp89 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
94 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
99 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
102 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
105 static DecodeStatus Decode2RInstruction(MCInst &Inst,
110 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
115 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
120 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
125 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
130 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
212 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
224 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
236 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
247 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
288 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
358 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
371 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
384 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
397 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
411 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
424 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
437 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
451 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
522 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
536 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
550 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
563 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
576 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
589 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
602 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
616 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
631 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
645 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
659 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
679 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
693 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
713 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
732 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64AddressTypePromotion.cpp106 /// - Inst is used only once (no need to insert truncate).
107 /// - Inst has only one operand that will require a sext operation (we do
109 bool shouldGetThrough(const Instruction *Inst);
117 bool canGetThrough(const Instruction *Inst);
154 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) { argument
155 if (isa<SExtInst>(Inst))
158 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
164 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
165 const Instruction *Opnd = cast<Instruction>(Inst
177 shouldGetThrough(const Instruction *Inst) argument
206 shouldSExtOperand(const Instruction *Inst, int OpIdx) argument
390 << *Inst << '\\n'); local
439 const Instruction *Inst = dyn_cast<GetElementPtrInst>(U); local
450 Instruction *Inst = SExt; local
[all...]
/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp51 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
57 Inst.addOperand(MCOperand::CreateReg(RegNo));
61 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
64 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
67 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
70 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
73 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
76 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
79 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
82 return decodeRegisterClass(Inst, RegN
[all...]
/external/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp51 Instruction *Inst; member in struct:__anon26276::SimpleValue
53 SimpleValue(Instruction *I) : Inst(I) {
54 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
58 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() ||
59 Inst == DenseMapInfo<Instruction*>::getTombstoneKey();
62 static bool canHandle(Instruction *Inst) { argument
64 if (CallInst *CI = dyn_cast<CallInst>(Inst))
66 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
67 isa<GetElementPtrInst>(Inst) || is
89 Instruction *Inst = Val.Inst; local
194 Instruction *Inst; member in struct:__anon26277::CallValue
205 canHandle(Instruction *Inst) argument
231 Instruction *Inst = Val.Inst; local
423 Instruction *Inst = I++; local
528 << *Inst << '\\n'); local
[all...]
H A DSink.cpp60 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
61 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
76 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument
82 for (Use &U : Inst->uses()) {
139 Instruction *Inst = I; // The instruction to sink. local
147 if (isa<DbgInfoIntrinsic>(Inst))
150 if (SinkInstruction(Inst, Stores))
159 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument
162 if (Inst->mayWriteToMemory()) {
163 Stores.insert(Inst);
183 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument
222 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument
[all...]
H A DConstantHoisting.cpp65 Instruction *Inst; member in struct:__anon26269::ConstantUser
68 ConstantUser(Instruction *Inst, unsigned Idx) : Inst(Inst), OpndIdx(Idx) { } argument
81 void addUser(Instruction *Inst, unsigned Idx, unsigned Cost) { argument
83 Uses.push_back(ConstantUser(Inst, Idx));
156 Instruction *findMatInsertPt(Instruction *Inst, unsigned Idx = ~0U) const;
159 Instruction *Inst, unsigned Idx,
162 Instruction *Inst);
210 Instruction *ConstantHoisting::findMatInsertPt(Instruction *Inst, argument
271 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst, unsigned Idx, ConstantInt *ConstInt) argument
308 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst) argument
441 updateOperand(Instruction *Inst, unsigned Idx, Instruction *Mat) argument
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigne
880 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
891 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
904 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
918 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
930 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
945 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
975 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
995 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1016 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1026 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1034 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1049 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1069 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1090 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1102 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1116 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1125 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1134 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1171 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1206 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1243 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1267 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1292 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1319 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1469 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1574 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1618 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1809 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1838 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1861 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1952 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1999 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2041 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2065 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2092 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2120 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2140 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2159 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2165 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2192 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2218 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2235 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2509 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2522 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2537 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2550 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2560 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2831 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2878 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2926 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2961 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3016 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3061 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3080 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3086 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3092 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3098 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3104 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3140 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3164 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3172 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3180 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3188 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3203 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3217 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3227 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3235 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3263 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3334 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3398 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3463 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3502 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3547 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3561 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3576 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument
3591 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3604 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3650 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3711 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3737 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3748 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3773 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3784 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3797 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3821 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3836 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3852 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3894 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3926 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3934 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3957 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3966 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3975 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3982 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4003 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4028 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4053 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4081 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4106 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4131 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4198 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4264 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4331 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4395 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4465 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4529 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4610 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4682 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4708 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4734 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4754 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4791 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4825 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
4840 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
4851 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4878 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4908 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4938 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4965 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
843 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
852 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
865 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
876 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
886 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
893 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
905 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
917 DecodeFGRH32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
929 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
940 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
951 DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
962 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
984 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1030 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1051 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1069 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1087 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1109 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1120 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1133 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1145 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1157 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1169 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1181 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1193 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1205 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1217 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1229 DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1241 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1250 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1260 DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1270 DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1280 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1289 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1298 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1306 DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1315 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1326 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1335 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1341 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp34 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
37 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
41 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
44 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
47 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
53 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
59 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
62 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
266 DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
277 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
295 DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
316 DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
337 DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
358 DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
379 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
390 DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
412 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
423 DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
446 DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
468 DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
491 DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
514 DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
535 DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
558 DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
581 DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
591 DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
600 DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
607 DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
623 DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
630 DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
647 DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
664 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
687 DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
693 DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
699 DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
704 DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
710 DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
715 DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
721 DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
726 DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
732 DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
737 DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
742 DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
747 DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
752 DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
757 DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
819 DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
852 DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
913 DecodeSignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1098 DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1173 DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1302 DecodeAddSubERegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1359 DecodeLogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1390 DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1429 DecodeModImmTiedInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1447 DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1466 DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1502 DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1519 DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1537 DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp313 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
314 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
316 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
317 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
358 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1693 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
1696 Inst.addOperand(MCOperand::CreateImm(0));
1698 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1700 Inst.addOperand(MCOperand::CreateExpr(Expr));
1703 void addCondCodeOperands(MCInst &Inst, unsigne argument
1710 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument
1715 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument
1720 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument
1725 addITMaskOperands(MCInst &Inst, unsigned N) const argument
1730 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument
1735 addCCOutOperands(MCInst &Inst, unsigned N) const argument
1740 addRegOperands(MCInst &Inst, unsigned N) const argument
1745 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument
1755 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument
1766 addShifterImmOperands(MCInst &Inst, unsigned N) const argument
1772 addRegListOperands(MCInst &Inst, unsigned N) const argument
1780 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument
1784 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument
1788 addRotImmOperands(MCInst &Inst, unsigned N) const argument
1794 addBitfieldOperands(MCInst &Inst, unsigned N) const argument
1805 addImmOperands(MCInst &Inst, unsigned N) const argument
1810 addFBits16Operands(MCInst &Inst, unsigned N) const argument
1816 addFBits32Operands(MCInst &Inst, unsigned N) const argument
1822 addFPImmOperands(MCInst &Inst, unsigned N) const argument
1829 addImm8s4Operands(MCInst &Inst, unsigned N) const argument
1837 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument
1845 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument
1853 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument
1861 addImm1_16Operands(MCInst &Inst, unsigned N) const argument
1869 addImm1_32Operands(MCInst &Inst, unsigned N) const argument
1877 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument
1886 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument
1895 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument
1903 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument
1911 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument
1919 addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const argument
1930 addThumbMemPCOperands(MCInst &Inst, unsigned N) const argument
1950 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument
1958 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument
1966 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1971 addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1976 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument
1981 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument
1987 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument
2003 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument
2009 addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2013 addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2017 addAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2021 addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2025 addAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2029 addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2033 addAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2037 addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2041 addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2045 addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2049 addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const argument
2053 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument
2271 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument
2278 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument
2285 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument
2292 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument
2303 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument
2315 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument
2321 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument
2332 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument
2337 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument
2342 addVecListOperands(MCInst &Inst, unsigned N) const argument
2347 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument
2353 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument
2358 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument
2363 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument
2368 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument
2376 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument
2388 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument
2402 addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2415 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument
2429 addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2442 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument
2456 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument
4384 cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) argument
4400 cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) argument
5277 RequiresVFPRegListValidation(StringRef Inst, bool &AcceptSinglePrecisionOnly, bool &AcceptDoublePrecisionOnly) argument
5591 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5607 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument
5618 instIsBreakpoint(const MCInst &Inst) argument
5627 validateInstruction(MCInst &Inst, const OperandVector &Operands) argument
6173 processInstruction(MCInst &Inst, const OperandVector &Operands) argument
7983 checkTargetMatchPredicate(MCInst &Inst) argument
8036 MCInst Inst; local
[all...]
/external/llvm/utils/TableGen/
H A DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
91 for (auto &Op : Inst.Operands) {
180 for (const CodeGenInstruction *Inst : Target.instructions()) {
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
208 for (const CodeGenInstruction *Inst : NumberedInstructions) {
209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
212 for (const auto &Info : Inst->Operands) {
221 OperandMap[OpList].push_back(Namespace + "::" + Inst
362 Record *Inst = II->TheDef; local
461 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
/external/llvm/lib/Transforms/ObjCARC/
H A DObjCARCExpand.cpp98 Instruction *Inst = &*I; local
100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
102 switch (GetBasicInstructionClass(Inst)) {
114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
117 Inst->replaceAllUsesWith(Value);
H A DDependencyAnalysis.cpp36 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument
49 ImmutableCallSite CS = static_cast<const Value *>(Inst);
73 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument
81 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
87 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) {
96 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
106 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end();
115 /// Test if there can be dependencies on Inst through Arg. This function only
118 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, argument
238 Instruction *Inst = --LocalStartPos; local
[all...]
H A DDependencyAnalysis.h61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
67 CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
73 CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
/external/llvm/lib/Analysis/
H A DPHITransAddr.cpp25 static bool CanPHITrans(Instruction *Inst) { argument
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr); local
119 return !Inst || CanPHITrans(Inst);
149 Instruction *Inst = dyn_cast<Instruction>(V); local
[all...]
H A DDelinearization.cpp73 static Value *getPointerOperand(Instruction &Inst) { argument
74 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
76 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
78 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
86 Instruction *Inst = &(*I); local
89 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
90 !isa<GetElementPtrInst>(Inst))
93 const BasicBlock *BB = Inst->getParent();
97 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst),
113 O << "Inst:" << *Inst << "\\n"; local
[all...]
H A DMemDepPrinter.cpp101 Instruction *Inst = &*I; local
103 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
106 MemDepResult Res = MDA.getDependency(Inst);
108 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
110 } else if (CallSite CS = cast<Value>(Inst)) {
114 DepSet &InstDeps = Deps[Inst];
122 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
125 Deps[Inst].insert(std::make_pair(getInstTypePair(nullptr, Unknown),
131 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
161 const Instruction *Inst = &*I; local
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_init.h80 lp_set_load_alignment(LLVMValueRef Inst,
84 lp_set_store_alignment(LLVMValueRef Inst,
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_init.h80 lp_set_load_alignment(LLVMValueRef Inst,
84 lp_set_store_alignment(LLVMValueRef Inst,
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp172 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
179 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
182 return decodeRegisterClass(Inst, RegNo, CRRegs);
185 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
188 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
191 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
194 return decodeRegisterClass(Inst, RegNo, FRegs);
197 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
200 return decodeRegisterClass(Inst, RegN
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp51 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
53 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
66 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
68 void EmitInstruction(MCStreamer &Out, const MCInst &Inst) { argument
69 Out.EmitInstruction(Inst, STI);
98 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
103 switch (Inst.getOpcode()) {
134 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
186 MCInst Inst; local
187 Inst
97 InstrumentMOV( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument
199 MCInst Inst; local
224 MCInst Inst; local
267 MCInst Inst; local
278 MCInst Inst; local
326 MCInst Inst; local
362 MCInst Inst; local
373 MCInst Inst; local
398 MCInst Inst; local
442 MCInst Inst; local
451 MCInst Inst; local
488 InstrumentInstruction( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument
[all...]

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