Searched refs:LWL (Results 1 - 11 of 11) sorted by relevance
| /external/chromium_org/v8/src/mips/ |
| H A D | constants-mips.cc | 313 case LWL:
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| H A D | constants-mips.h | 346 LWL = ((4 << 3) + 2) << kOpcodeShift,
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| H A D | simulator-mips.cc | 2853 case LWL: {
2965 case LWL:
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| H A D | assembler-mips.cc | 1717 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
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| /external/chromium_org/v8/src/mips64/ |
| H A D | constants-mips64.cc | 331 case LWL:
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| H A D | constants-mips64.h | 315 LWL = ((4 << 3) + 2) << kOpcodeShift,
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| H A D | simulator-mips64.cc | 2842 // Alignment for 32-bit integers used in LWL, LWR, etc.
2992 case LWL: {
3116 case LWL:
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| H A D | assembler-mips64.cc | 1854 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 221 case Mips::LWL:
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator in enum:llvm::MipsISD::NodeType
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| H A D | MipsISelLowering.cpp | 155 case MipsISD::LWL: return "MipsISD::LWL";
2055 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, local
2057 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
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