Searched refs:MRI (Results 1 - 25 of 247) sorted by relevance

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/external/llvm/include/llvm/MC/MCAnalysis/
H A DMCModuleYAML.h31 const MCInstrInfo &MII, const MCRegisterInfo &MRI);
36 const MCInstrInfo &MII, const MCRegisterInfo &MRI);
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp65 MachineRegisterInfo *MRI; member in class:__anon25930::AArch64AdvSIMDScalar
101 const MachineRegisterInfo *MRI) {
105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
110 const MachineRegisterInfo *MRI) {
112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
124 const MachineRegisterInfo *MRI,
141 MRI) &&
142 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
145 MRI)
100 isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument
109 isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument
123 getSrcFromCopy(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument
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/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp88 const MachineRegisterInfo &MRI,
92 const MachineRegisterInfo &MRI,
96 const MachineRegisterInfo &MRI) const;
118 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local
124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
135 const MachineRegisterInfo &MRI,
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
133 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
159 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
197 MachineRegisterInfo &MRI = MF.getRegInfo(); local
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H A DSIMachineFunctionInfo.cpp32 static unsigned createLaneVGPR(MachineRegisterInfo &MRI, MachineFunction *MF) { argument
33 unsigned VGPR = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
73 MachineRegisterInfo &MRI, MachineFunction *MF, unsigned NumRegs) {
77 LaneVGPR = createLaneVGPR(MRI, MF);
81 LaneVGPR = createLaneVGPR(MRI, MF);
72 reserveLanes( MachineRegisterInfo &MRI, MachineFunction *MF, unsigned NumRegs) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI
122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument
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H A DSIISelLowering.h33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI
122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument
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H A DSIISelLowering.h33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.h37 const MCRegisterInfo &MRI,
41 const MCRegisterInfo &MRI,
46 const MCRegisterInfo &MRI, StringRef TT,
49 const MCRegisterInfo &MRI, StringRef TT,
52 const MCRegisterInfo &MRI, StringRef TT,
55 const MCRegisterInfo &MRI, StringRef TT,
/external/llvm/lib/CodeGen/
H A DRegAllocBase.cpp61 MRI = &vrm.getRegInfo();
65 MRI->freezeReservedRegs(vrm.getMachineFunction());
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
76 if (MRI->reg_nodbg_empty(Reg))
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
105 << MRI->getRegClass(VirtReg->reg)->getName()
116 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
141 if (MRI
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H A DOptimizePHIs.cpp32 MachineRegisterInfo *MRI; member in class:__anon25781::OptimizePHIs
68 MRI = &Fn.getRegInfo();
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
113 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
173 MRI->replaceRegWith(OldReg, SingleValReg);
H A DPHIEliminationUtils.cpp36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); local
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
H A DRegAllocBase.h62 MachineRegisterInfo *MRI; member in class:llvm::RegAllocBase
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h38 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI, StringRef TT,
45 const MCRegisterInfo &MRI, StringRef TT,
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUMCTargetDesc.h35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
43 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
H A DAMDGPUMCTargetDesc.cpp69 const MCRegisterInfo &MRI,
71 return new AMDGPUInstPrinter(MAI, MII, MRI);
75 const MCRegisterInfo &MRI,
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI);
65 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
74 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.h14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
13 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.h14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
13 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h57 const MCRegisterInfo &MRI,
62 const MCRegisterInfo &MRI,
66 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
70 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
73 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
76 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
79 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
/external/llvm/lib/Target/MSP430/InstPrinter/
H A DMSP430InstPrinter.h25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
24 MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.h39 const MCRegisterInfo &MRI,
43 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.h35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
/external/llvm/lib/Target/XCore/InstPrinter/
H A DXCoreInstPrinter.h27 const MCRegisterInfo &MRI)
28 : MCInstPrinter(MAI, MII, MRI) {}
26 XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp112 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local
113 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
126 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
127 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
191 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) argument
195 if (MRI->isPhysRegUsed(reg))
199 if (MRI->isPhysRegUsed(reg))
208 MachineRegisterInfo &MRI = MF.getRegInfo(); local
212 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
213 || MRI
219 MachineRegisterInfo &MRI = MF.getRegInfo(); local
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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h70 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
80 const MCRegisterInfo &MRI,
84 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
86 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,

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