/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 29 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), 47 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 70 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 71 (Opc == Mips [all...] |
H A D | MipsRegisterInfo.cpp | 15 #include "Mips.h" 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 53 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 62 case Mips::GPR32RegClassID: 63 case Mips::GPR64RegClassID: 64 case Mips::DSPRRegClassID: { 68 case Mips::FGR32RegClassID: 70 case Mips [all...] |
H A D | Mips16InstrInfo.cpp | 35 : MipsInstrInfo(tm, Mips::Bimm16), 70 if (Mips::CPU16RegsRegClass.contains(DestReg) && 71 Mips::GPR32RegClass.contains(SrcReg)) 72 Opc = Mips::MoveR3216; 73 else if (Mips::GPR32RegClass.contains(DestReg) && 74 Mips::CPU16RegsRegClass.contains(SrcReg)) 75 Opc = Mips::Move32R16; 76 else if ((SrcReg == Mips::HI0) && 77 (Mips::CPU16RegsRegClass.contains(DestReg))) 78 Opc = Mips [all...] |
H A D | MipsSERegisterInfo.cpp | 16 #include "Mips.h" 60 return &Mips::GPR32RegClass; 63 return &Mips::GPR64RegClass; 71 case Mips::LD_B: 72 case Mips::ST_B: 74 case Mips::LD_H: 75 case Mips::ST_H: 77 case Mips::LD_W: 78 case Mips::ST_W: 80 case Mips [all...] |
H A D | MipsRelocations.h | 1 //===-- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===// 10 // This file defines the Mips target-specific relocation types 21 namespace Mips{ namespace in namespace:llvm
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H A D | MipsLongBranch.cpp | 16 #include "Mips.h" 72 return "Mips Long Branch"; 274 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; 293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 294 .addReg(Mips::SP).addImm(-8); 295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 296 .addReg(Mips [all...] |
H A D | Mips16ISelLowering.cpp | 31 "pseudos for Mips 16"), 125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 170 case Mips::SelBeqZ: 171 return emitSel16(Mips::BeqzRxImm16, MI, BB); 172 case Mips::SelBneZ: 173 return emitSel16(Mips::BnezRxImm16, MI, BB); 174 case Mips::SelTBteqZCmpi: 175 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); 176 case Mips [all...] |
H A D | MipsAsmPrinter.cpp | 1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===// 18 #include "Mips.h" 103 TmpInst0.setOpcode(Mips::JALR64); 107 TmpInst0.setOpcode(Mips::JALR); 111 TmpInst0.setOpcode(Mips::JR_MM); 114 TmpInst0.setOpcode(Mips::JR); 120 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 143 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) { 147 if (MI->getOpcode() == Mips [all...] |
H A D | MipsCodeEmitter.cpp | 1 //===-- Mips/MipsCodeEmitter.cpp - Convert Mips Code to Machine Code ------===// 10 // This file contains the pass that transforms the Mips machine instructions 15 #include "Mips.h" 76 return "Mips Machine Code Emitter"; 178 return Mips::reloc_mips_26; 181 return Mips::reloc_mips_pc16; 182 if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi) 183 return Mips::reloc_mips_hi; 184 return Mips [all...] |
H A D | MipsFastISel.cpp | 1 //===-- MipsastISel.cpp - Mips FastISel implementation 163 ResultReg = createResultReg(&Mips::GPR32RegClass); 164 Opc = Mips::LW; 168 ResultReg = createResultReg(&Mips::GPR32RegClass); 169 Opc = Mips::LHu; 173 ResultReg = createResultReg(&Mips::GPR32RegClass); 174 Opc = Mips::LBu; 178 ResultReg = createResultReg(&Mips::FGR32RegClass); 179 Opc = Mips::LWC1; 183 ResultReg = createResultReg(&Mips [all...] |
H A D | MipsSEFrameLowering.cpp | 37 if (Mips::ACC64RegClass.contains(Src)) 38 return std::make_pair((unsigned)Mips::PseudoMFHI, 39 (unsigned)Mips::PseudoMFLO); 41 if (Mips::ACC64DSPRegClass.contains(Src)) 42 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); 44 if (Mips::ACC128RegClass.contains(Src)) 45 return std::make_pair((unsigned)Mips::PseudoMFHI64, 46 (unsigned)Mips::PseudoMFLO64); 89 case Mips [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 16 #include "Mips.h" 52 MIB.addReg(Mips::DSPPos, Flag); 55 MIB.addReg(Mips::DSPSCount, Flag); 58 MIB.addReg(Mips::DSPCarry, Flag); 61 MIB.addReg(Mips::DSPOutFlag, Flag); 64 MIB.addReg(Mips::DSPCCond, Flag); 67 MIB.addReg(Mips::DSPEFI, Flag); 74 case 0: return Mips::MSAIR; 75 case 1: return Mips::MSACSR; 76 case 2: return Mips [all...] |
H A D | MipsConstantIslandPass.cpp | 24 #include "Mips.h" 82 case Mips::Bimm16: 83 case Mips::BimmX16: 84 case Mips::Bteqz16: 85 case Mips::BteqzX16: 86 case Mips::Btnez16: 87 case Mips::BtnezX16: 88 case Mips::JalB16: 90 case Mips::BeqzRxImm16: 91 case Mips [all...] |
H A D | Mips16FrameLowering.cpp | 52 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); 77 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0) 78 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup); 95 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP) 96 .addReg(Mips::S0); 100 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI); 123 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 153 if (I->getOpcode() == Mips [all...] |
H A D | Mips16ISelDAGToDAG.cpp | 16 #include "Mips.h" 54 unsigned Opcode = Mips::Mflo16; 59 unsigned Opcode = Mips::Mfhi16; 78 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0). 89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); 90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg) 109 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg) 110 .addReg(Mips::SP); 128 SDValue AliasFPReg = CurDAG->getRegister(Mips [all...] |
H A D | MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 60 Mips::A0, Mips::A1, Mips::A2, Mips::A3 64 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips [all...] |
H A D | Mips16RegisterInfo.cpp | 15 #include "Mips.h" 69 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); 70 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); 77 return &Mips::CPU16RegsRegClass; 107 FrameReg = Mips::SP; 111 FrameReg = Mips::S0; 117 FrameReg = Mips::SP;
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsELFObjectWriter.cpp | 1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===// 70 case Mips::fixup_Mips_GPREL16: 73 case Mips::fixup_Mips_26: 76 case Mips::fixup_Mips_CALL16: 79 case Mips::fixup_Mips_GOT_Global: 80 case Mips::fixup_Mips_GOT_Local: 83 case Mips::fixup_Mips_HI16: 86 case Mips::fixup_Mips_LO16: 89 case Mips::fixup_Mips_TLSGD: 92 case Mips [all...] |
H A D | MipsNaClELFStreamer.cpp | 1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===// 10 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files 20 #include "Mips.h" 31 const unsigned IndirectBranchMaskReg = Mips::T6; 32 const unsigned LoadStoreStackMaskReg = Mips::T7; 51 if (MI.getOpcode() == Mips::JALR) { 55 return MI.getOperand(0).getReg() == Mips::ZERO; 57 return MI.getOpcode() == Mips::JR; 62 && MI.getOperand(0).getReg() == Mips::SP); 74 case Mips [all...] |
H A D | MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 70 case Mips::DSLL: 71 Inst.setOpcode(Mips::DSLL32); 73 case Mips::DSRL: 74 Inst.setOpcode(Mips::DSRL32); 76 case Mips::DSRA: 77 Inst.setOpcode(Mips::DSRA32); 79 case Mips::DROTR: 80 Inst.setOpcode(Mips::DROTR32); 89 if (Opcode == Mips [all...] |
H A D | MipsAsmBackend.cpp | 1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips [all...] |
H A D | MipsTargetStreamer.cpp | 1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===// 10 // This file provides Mips specific target streamer methods. 261 if (Features & Mips::FeatureMips64r6) 263 else if (Features & Mips::FeatureMips64r2) 265 else if (Features & Mips::FeatureMips64) 267 else if (Features & Mips::FeatureMips5) 269 else if (Features & Mips::FeatureMips4) 271 else if (Features & Mips::FeatureMips3) 273 else if (Features & Mips::FeatureMips32r6) 275 else if (Features & Mips [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// 10 // This class prints an Mips MCInst to a .s file. 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { 84 case Mips::RDHWR: 85 case Mips::RDHWR64: 89 case Mips::Save16: 94 case Mips::SaveX16: 99 case Mips::Restore16: 104 case Mips [all...] |
/external/llvm/host/include/llvm/Config/ |
H A D | Targets.def | 27 LLVM_TARGET(Mips)
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/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 10 // This file is part of the Mips Disassembler. 14 #include "Mips.h" 34 /// MipsDisassemblerBase - a disasembler class for Mips. 42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} 62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 68 return STI.getFeatureBits() & Mips::FeatureMips32r6; 71 bool isGP64() const { return STI.getFeatureBits() & Mips [all...] |