Searched refs:NewOpc (Results 1 - 25 of 29) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp488 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
489 MI.setDesc(TII.get(NewOpc));
522 unsigned NewOpc = Opcode;
532 NewOpc = immediateOffsetOpcode(Opcode);
544 NewOpc = negativeOffsetOpcode(Opcode);
549 NewOpc = positiveOffsetOpcode(Opcode);
579 if (NewOpc != Opcode)
580 MI.setDesc(TII.get(NewOpc));
613 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
H A DARMLoadStoreOptimizer.cpp1052 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local
1053 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
1155 unsigned NewOpc = 0; local
1173 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
1192 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
1210 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
1219 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
1221 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
1226 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), M
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1421 unsigned NewOpc = (isLd) local
1444 unsigned NewOpc = (isLd) local
1713 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); local
1875 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
2040 unsigned NewOpc = 0; local
[all...]
H A DARMConstantIslandPass.cpp1701 unsigned NewOpc = 0; local
1708 NewOpc = ARM::tLEApcrel;
1715 NewOpc = ARM::tLDRpci;
1722 if (!NewOpc)
1735 U.MI->setDesc(TII->get(NewOpc));
1755 unsigned NewOpc = 0; local
1761 NewOpc = ARM::tB;
1766 NewOpc = ARM::tBcc;
1772 if (NewOpc) {
1777 Br.MI->setDesc(TII->get(NewOpc));
[all...]
H A DARMExpandPseudoInsts.cpp802 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; local
803 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
841 unsigned NewOpc; local
843 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
844 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
845 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
846 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
849 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1082 unsigned NewOpc = ARM::VLDMDIA; local
1084 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1113 unsigned NewOpc = ARM::VSTMDIA; local
[all...]
H A DARMISelLowering.cpp2605 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local
2607 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
5814 unsigned NewOpc = 0; local
5819 NewOpc = ARMISD::VMULLs;
5824 NewOpc = ARMISD::VMULLu;
5829 NewOpc = ARMISD::VMULLs;
5832 NewOpc = ARMISD::VMULLu;
5836 NewOpc = ARMISD::VMULLu;
5841 if (!NewOpc) {
5860 return DAG.getNode(NewOpc, D
7252 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? local
7276 unsigned NewOpc; local
7497 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); local
8850 unsigned NewOpc = 0; local
8968 unsigned NewOpc = 0; local
[all...]
H A DThumb1RegisterInfo.cpp460 unsigned NewOpc = convertToNonSPOpcode(Opcode); variable
461 if (NewOpc != Opcode && FrameReg != ARM::SP)
462 MI.setDesc(TII.get(NewOpc));
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp421 unsigned NewOpc; local
424 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
425 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
426 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
427 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
428 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
429 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
430 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
431 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
432 case X86::VMOVUPDrr: NewOpc
445 unsigned NewOpc; local
[all...]
H A DX86InstrInfo.cpp3726 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3792 unsigned NewOpc; local
3794 NewOpc = GetCondBranchFromCond(NewCC);
3796 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3799 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3806 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4356 unsigned NewOpc = 0; local
4360 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4361 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4362 case X86::TEST32rr: NewOpc
4424 unsigned NewOpc = 0; local
4674 unsigned NewOpc; local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp709 unsigned NewOpc; local
713 case AArch64::ADDSWrr: NewOpc = AArch64::ADDWrr; break;
714 case AArch64::ADDSWri: NewOpc = AArch64::ADDWri; break;
715 case AArch64::ADDSWrs: NewOpc = AArch64::ADDWrs; break;
716 case AArch64::ADDSWrx: NewOpc = AArch64::ADDWrx; break;
717 case AArch64::ADDSXrr: NewOpc = AArch64::ADDXrr; break;
718 case AArch64::ADDSXri: NewOpc = AArch64::ADDXri; break;
719 case AArch64::ADDSXrs: NewOpc = AArch64::ADDXrs; break;
720 case AArch64::ADDSXrx: NewOpc = AArch64::ADDXrx; break;
721 case AArch64::SUBSWrr: NewOpc
784 unsigned NewOpc = MI->getOpcode(); local
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H A DAArch64AdvSIMDScalarPass.cpp283 int NewOpc = getTransformOpcode(OldOpc); local
284 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
H A DAArch64LoadStoreOptimizer.cpp286 unsigned NewOpc = getMatchingPairOpcode(I->getOpcode()); local
312 I->getDebugLoc(), TII->get(NewOpc))
538 unsigned NewOpc = getPreIndexedOpcode(I->getOpcode()); local
540 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
581 unsigned NewOpc = getPostIndexedOpcode(I->getOpcode()); local
583 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
H A DAArch64ISelLowering.cpp7478 unsigned NewOpc = 0; local
7483 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7485 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7487 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7489 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7491 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7493 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7495 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7497 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7499 case Intrinsic::aarch64_neon_ld1x4: NewOpc
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h90 unsigned NewOpc) const;
H A DMipsInstrInfo.h122 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
H A DMipsSEISelLowering.h66 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
H A DMipsInstrInfo.cpp285 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument
288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
H A DMipsLongBranch.cpp221 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); local
222 const MCInstrDesc &NewDesc = TII->get(NewOpc);
H A DMipsSEInstrInfo.cpp455 unsigned NewOpc) const {
456 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp2242 unsigned NewOpc; local
2245 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2246 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2247 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2248 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2249 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2250 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2251 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2252 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2253 case X86::VMOVUPDrr: NewOpc
2266 unsigned NewOpc; local
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp420 unsigned NewOpc; local
425 NewOpc = ISD::FP_TO_SINT;
429 NewOpc = ISD::FP_TO_UINT;
435 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7324 unsigned NewOpc; local
7327 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7328 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7329 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7333 TmpInst.setOpcode(NewOpc);
7798 unsigned NewOpc; local
7801 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7802 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7803 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7804 case ARM::t2UXTB: NewOpc
7913 unsigned NewOpc; local
7953 unsigned NewOpc; local
[all...]
/external/llvm/lib/CodeGen/
H A DMachineLICM.cpp1254 unsigned NewOpc = local
1259 if (NewOpc == 0) return nullptr;
1260 const MCInstrDesc &MID = TII->get(NewOpc);
/external/llvm/lib/Target/R600/
H A DSIInstrInfo.cpp172 int NewOpc; local
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
176 return NewOpc;
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
180 return NewOpc;

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