/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 76 int NewOpcode = 0; local 79 NewOpcode = Hexagon::JMP_f; 83 NewOpcode = Hexagon::JMP_t; 87 NewOpcode = Hexagon::JMP_fnew_t; 91 NewOpcode = Hexagon::JMP_tnew_t; 98 MI->setDesc(QII->get(NewOpcode));
|
H A D | HexagonVLIWPacketizer.cpp | 439 int NewOpcode; local 441 NewOpcode = QII->GetDotNewPredOp(MI, MBPI); 443 NewOpcode = QII->GetDotNewOp(MI); 444 MI->setDesc(QII->get(NewOpcode)); 451 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); local 452 MI->setDesc(QII->get(NewOpcode)); 772 int NewOpcode = QII->GetDotNewOp(MI); local 773 const MCInstrDesc &desc = QII->get(NewOpcode);
|
H A D | HexagonInstrInfo.cpp | 1585 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); local 1586 if (NewOpcode >= 0) // Valid predicate new instruction 1587 return NewOpcode;
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 137 int NewOpcode; local 139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
|
/external/llvm/lib/Target/R600/ |
H A D | AMDILCFGStructurizer.cpp | 228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, 230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, 232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode); 233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode, 236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, 238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum); 469 int NewOpcode, DebugLoc DL) { 471 ->CreateMachineInstr(TII->get(NewOpcode), DL); 478 int NewOpcode, DebugLoc DL) { 480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), D 468 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument 477 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument 489 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument 501 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, DebugLoc DL) argument 514 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument 525 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument [all...] |
H A D | SIISelLowering.cpp | 1671 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); local 1672 MI->setDesc(TII->get(NewOpcode)); 1681 unsigned NewOpcode = N->getMachineOpcode(); local 1686 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64; 1689 if (NewOpcode == N->getMachineOpcode()) { 1690 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; 1695 if (NewOpcode == N->getMachineOpcode()) { 1696 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; 1708 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
|
H A D | SIInstrInfo.cpp | 1116 unsigned NewOpcode = getVALUOp(*MI); local 1162 MI->setDesc(get(NewOpcode)); 1183 unsigned NewOpcode = getVALUOp(*Inst); local 1247 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { 1255 const MCInstrDesc &NewDesc = get(NewOpcode);
|
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 427 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local 431 if (!NewOpcode) { 436 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 437 assert(NewOpcode && "No restore instruction available"); 440 MBBI->setDesc(ZII->get(NewOpcode));
|
H A D | SystemZInstrInfo.cpp | 49 // each having the opcode given by NewOpcode. 51 unsigned NewOpcode) const { 73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local 92 assert(NewOpcode && "No support for huge argument lists yet"); 93 MI->setDesc(get(NewOpcode)); 725 unsigned NewOpcode; local 727 NewOpcode = SystemZ::RISBG; 729 NewOpcode [all...] |
H A D | SystemZInstrInfo.h | 118 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
|
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); 181 if (NewOpcode != -1) { 184 Opcode = NewOpcode; 185 TmpInst.setOpcode (NewOpcode);
|
/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 263 unsigned NewOpcode = 0; local 270 NewOpcode = X86::CBW; 274 NewOpcode = X86::CWDE; 278 NewOpcode = X86::CDQE; 282 if (NewOpcode != 0) { 284 Inst.setOpcode(NewOpcode);
|
H A D | X86InstrInfo.cpp | 3584 unsigned NewOpcode = 0; local 3607 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3608 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3609 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3610 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3611 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3612 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3613 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3614 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3615 case X86::SUB64ri32: NewOpcode [all...] |
/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 1350 std::string NewOpcode; local 1353 NewOpcode = Name; 1354 NewOpcode += '+'; 1355 Name = NewOpcode; 1359 NewOpcode = Name; 1360 NewOpcode += '-'; 1361 Name = NewOpcode; 1367 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1375 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCAsmPrinter.cpp | 669 unsigned NewOpcode = local 673 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) 683 unsigned NewOpcode = local 689 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
|
H A D | PPCRegisterInfo.cpp | 821 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local 822 MI.setDesc(TII.get(NewOpcode));
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 3773 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 3777 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 3785 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 3789 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
|