Searched refs:NumSuccs (Results 1 - 6 of 6) sorted by relevance

/external/llvm/lib/CodeGen/
H A DScheduleDAGPrinter.cpp44 return (Node->NumPreds > 10 || Node->NumSuccs > 10);
H A DScheduleDAG.cpp100 assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
102 ++N->NumSuccs;
151 assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
153 --N->NumSuccs;
389 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
H A DScheduleDAGInstrs.cpp836 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
838 if (SU->NumSuccs == 0 && SU->Latency > 1
/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp146 unsigned NumSuccs = MBB->succ_size(); local
175 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) {
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h280 unsigned NumSuccs; // # of SDep::Data sucss. variable
321 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
337 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
352 NodeNum(BoundaryID), NodeQueueId(0), NumPreds(0), NumSuccs(0),
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1897 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1904 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1968 if (!N->isMachineOpcode() || !SU->NumSuccs)
2015 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
2124 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
2164 if (SU->NumSuccs && N->isMachineOpcode()) {
2590 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2815 if (SU->NumSuccs != 0)
2843 if (PredSU->NumSuccs == 1)
2860 if (PredSuccSU->NumSuccs
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