Searched refs:OL (Results 1 - 25 of 60) sorted by relevance

123

/external/llvm/lib/MC/
H A DMCCodeGenInfo.cpp19 CodeGenOpt::Level OL) {
22 OptLevel = OL;
18 InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp32 CodeGenOpt::Level OL,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
87 CodeGenOpt::Level OL)
88 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
99 CodeGenOpt::Level OL)
100 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcTargetMachine.h29 CodeGenOpt::Level OL, bool is64bit);
66 CodeGenOpt::Level OL);
78 CodeGenOpt::Level OL);
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp52 CodeGenOpt::Level OL, bool isLittle)
53 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
76 CodeGenOpt::Level OL, bool isLittle)
77 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
90 CodeGenOpt::Level OL)
91 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
99 CodeGenOpt::Level OL)
100 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
108 CodeGenOpt::Level OL, bool isLittle)
109 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
48 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
73 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
86 ARMLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
95 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
104 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
125 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...]
H A DARMTargetMachine.h32 CodeGenOpt::Level OL,
75 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
86 CodeGenOpt::Level OL);
96 CodeModel::Model CM, CodeGenOpt::Level OL);
108 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
119 CodeGenOpt::Level OL);
130 CodeGenOpt::Level OL);
/external/llvm/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp31 CodeGenOpt::Level OL)
32 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMSP430TargetMachine.h33 CodeGenOpt::Level OL);
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp43 CodeGenOpt::Level OL, bool is64Bit)
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
55 CodeGenOpt::Level OL)
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
65 CodeGenOpt::Level OL)
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
40 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
51 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
61 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DPPCTargetMachine.h33 CodeGenOpt::Level OL, bool is64Bit);
77 CodeGenOpt::Level OL);
88 CodeGenOpt::Level OL);
/external/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp57 CodeGenOpt::Level OL, bool isLittle)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
69 CodeGenOpt::Level OL)
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
78 CodeGenOpt::Level OL)
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
53 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
66 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
75 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMipsTargetMachine.h33 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
80 CodeGenOpt::Level OL);
91 CodeGenOpt::Level OL);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp73 CodeGenOpt::Level OL, bool is64bit)
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 CodeGenOpt::Level OL)
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
92 CodeGenOpt::Level OL)
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DNVPTXTargetMachine.h86 CodeGenOpt::Level OL);
95 CodeGenOpt::Level OL);
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.h32 CodeGenOpt::Level OL, bool IsLittleEndian);
71 CodeGenOpt::Level OL);
82 CodeGenOpt::Level OL);
/external/llvm/include/llvm/MC/
H A DMCCodeGenInfo.h38 CodeGenOpt::Level OL = CodeGenOpt::Default);
/external/llvm/lib/Target/CppBackend/
H A DCPPTargetMachine.h28 CodeGenOpt::Level OL)
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp71 CodeGenOpt::Level OL) {
75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp55 CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp26 CodeGenOpt::Level OL)
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSystemZTargetMachine.h32 CodeGenOpt::Level OL);
/external/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp27 CodeGenOpt::Level OL)
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DXCoreTargetMachine.h28 CodeGenOpt::Level OL);
/external/llvm/lib/Target/Hexagon/
H A DHexagonTargetMachine.h32 CodeGenOpt::Level OL);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp58 CodeGenOpt::Level OL) {
60 X->InitMCCodeGenInfo(RM, CM, OL);
56 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCTargetDesc.cpp55 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument

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