| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 223 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
474 case OP_ABS:
628 case OP_ABS:
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| H A D | nv50_ir_emit_nvc0.cpp | 809 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
825 if (neg && i->op != OP_ABS)
1659 case OP_ABS:
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 223 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
474 case OP_ABS:
628 case OP_ABS:
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| H A D | nv50_ir_emit_nvc0.cpp | 809 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
825 if (neg && i->op != OP_ABS)
1659 case OP_ABS:
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_peephole.cpp | 300 case OP_ABS:
377 case NV50_IR_MOD_ABS: return OP_ABS;
529 case OP_ABS: res.data.f32 = fabsf(imm.reg.data.f32); break;
807 case OP_ABS:
861 (mi->op != OP_ABS &&
872 if ((i->op == OP_ABS) || i->src(s).mod.abs()) {
1193 if (!insn || insn->op != OP_ABS || insn->sType != TYPE_S32 ||
1218 case OP_ABS:
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| H A D | nv50_ir_target_nv50.cpp | 91 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
409 case OP_ABS:
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| H A D | nv50_ir_lowering_nv50.cpp | 407 bld.mkOp1(OP_ABS, ty, a, div->getSrc(0));
408 bld.mkOp1(OP_ABS, ty, b, div->getSrc(1));
790 bld.mkOp1(OP_ABS, TYPE_S32, i->getDef(0), i->getDef(0));
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| H A D | nv50_ir_emit_nv50.cpp | 1209 case OP_ABS: code[1] |= 1 << 20; break;
1220 assert(i->op != OP_ABS || !i->src(0).mod.neg());
1608 case OP_ABS:
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| H A D | nv50_ir_from_tgsi.cpp | 1233 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1591 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1808 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1871 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
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| H A D | nv50_ir.cpp | 38 case OP_ABS: bits = NV50_IR_MOD_ABS; break;
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| H A D | nv50_ir.h | 59 OP_ABS, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_from_sm4.cpp | 1362 res = mkOp1v(OP_ABS, sTy, getSSA(res->reg.size), res);
1607 src0[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_peephole.cpp | 300 case OP_ABS:
377 case NV50_IR_MOD_ABS: return OP_ABS;
529 case OP_ABS: res.data.f32 = fabsf(imm.reg.data.f32); break;
807 case OP_ABS:
861 (mi->op != OP_ABS &&
872 if ((i->op == OP_ABS) || i->src(s).mod.abs()) {
1193 if (!insn || insn->op != OP_ABS || insn->sType != TYPE_S32 ||
1218 case OP_ABS:
|
| H A D | nv50_ir_target_nv50.cpp | 91 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
409 case OP_ABS:
|
| H A D | nv50_ir_lowering_nv50.cpp | 407 bld.mkOp1(OP_ABS, ty, a, div->getSrc(0));
408 bld.mkOp1(OP_ABS, ty, b, div->getSrc(1));
790 bld.mkOp1(OP_ABS, TYPE_S32, i->getDef(0), i->getDef(0));
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| H A D | nv50_ir_emit_nv50.cpp | 1209 case OP_ABS: code[1] |= 1 << 20; break;
1220 assert(i->op != OP_ABS || !i->src(0).mod.neg());
1608 case OP_ABS:
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| H A D | nv50_ir_from_tgsi.cpp | 1233 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1591 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1808 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1871 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
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| H A D | nv50_ir.cpp | 38 case OP_ABS: bits = NV50_IR_MOD_ABS; break;
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| H A D | nv50_ir.h | 59 OP_ABS, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_from_sm4.cpp | 1362 res = mkOp1v(OP_ABS, sTy, getSSA(res->reg.size), res);
1607 src0[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
|