| /external/apache-xml/src/main/java/org/apache/xpath/compiler/ |
| H A D | OpCodes.java | 94 * [OP_AND]
103 public static final int OP_AND = 3; field in class:OpCodes
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| H A D | Compiler.java | 127 case OpCodes.OP_AND :
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| H A D | XPathParser.java | 839 insertOp(opPos, 2, OpCodes.OP_AND);
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| /external/chromium_org/third_party/angle/src/compiler/preprocessor/ |
| H A D | Token.h | 37 OP_AND, enumerator in enum:pp::Token::Type
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| H A D | ExpressionParser.y | 219 case pp::Token::OP_AND:
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| H A D | Tokenizer.l | 168 return pp::Token::OP_AND;
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| H A D | ExpressionParser.cpp | 1915 case pp::Token::OP_AND:
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| /external/chromium_org/third_party/angle/tests/preprocessor_tests/ |
| H A D | operator_test.cpp | 63 {"&&", pp::Token::OP_AND},
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 229 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
480 case OP_AND:
615 case OP_AND:
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| H A D | nv50_ir_lowering_nvc0.cpp | 677 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
687 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
912 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 229 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
480 case OP_AND:
615 case OP_AND:
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| H A D | nv50_ir_lowering_nvc0.cpp | 677 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
687 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
912 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
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| /external/chromium_org/base/test/ |
| H A D | trace_event_analyzer.h | 452 OP_AND, enumerator in enum:trace_analyzer::Query::Operator
526 return operator_ != OP_INVALID && operator_ < OP_AND;
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| H A D | trace_event_analyzer.cc | 276 case OP_AND:
577 return Query(*this, rhs, OP_AND);
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
415 case OP_AND:
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| H A D | nv50_ir_lowering_nv50.cpp | 908 bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
929 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff));
931 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000));
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| H A D | nv50_ir_peephole.cpp | 466 case OP_AND:
756 i->op = OP_AND;
1118 if ((logop->op == OP_AND || logop->op == OP_OR) &&
1137 operation redOp = (logop->op == OP_AND ? OP_SET_AND :
1234 case OP_AND:
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| H A D | nv50_ir_emit_nv50.cpp | 1284 assert(i->op == OP_AND);
1293 case OP_AND: code[1] = 0x04000000; break;
1589 case OP_AND:
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| H A D | nv50_ir.h | 62 OP_AND, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_from_sm4.cpp | 356 case SM4_OPCODE_AND: return OP_AND;
465 case SM4_OPCODE_ATOMIC_AND: return OP_AND;
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
415 case OP_AND:
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| H A D | nv50_ir_lowering_nv50.cpp | 908 bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
929 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff));
931 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000));
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| H A D | nv50_ir_peephole.cpp | 466 case OP_AND:
756 i->op = OP_AND;
1118 if ((logop->op == OP_AND || logop->op == OP_OR) &&
1137 operation redOp = (logop->op == OP_AND ? OP_SET_AND :
1234 case OP_AND:
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| H A D | nv50_ir_emit_nv50.cpp | 1284 assert(i->op == OP_AND);
1293 case OP_AND: code[1] = 0x04000000; break;
1589 case OP_AND:
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| H A D | nv50_ir.h | 62 OP_AND, enumerator in enum:nv50_ir::operation
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