| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 102 { OP_LG2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
492 case OP_LG2:
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| H A D | nv50_ir.h | 82 OP_LG2, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_peephole.cpp | 532 case OP_LG2: res.data.f32 = log2f(imm.reg.data.f32); break;
809 case OP_LG2:
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| H A D | nv50_ir_lowering_nv50.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
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| H A D | nv50_ir_emit_nv50.cpp | 1630 case OP_LG2:
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| H A D | nv50_ir_from_sm4.cpp | 401 case SM4_OPCODE_LOG: return OP_LG2;
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| H A D | nv50_ir_from_tgsi.cpp | 1872 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 241 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
603 case OP_LG2:
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| H A D | nv50_ir_lowering_nvc0.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
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| H A D | nv50_ir_emit_nvc0.cpp | 1674 case OP_LG2:
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 102 { OP_LG2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
492 case OP_LG2:
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| H A D | nv50_ir.h | 82 OP_LG2, enumerator in enum:nv50_ir::operation
|
| H A D | nv50_ir_peephole.cpp | 532 case OP_LG2: res.data.f32 = log2f(imm.reg.data.f32); break;
809 case OP_LG2:
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| H A D | nv50_ir_lowering_nv50.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
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| H A D | nv50_ir_emit_nv50.cpp | 1630 case OP_LG2:
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| H A D | nv50_ir_from_sm4.cpp | 401 case SM4_OPCODE_LOG: return OP_LG2;
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| H A D | nv50_ir_from_tgsi.cpp | 1872 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 241 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
603 case OP_LG2:
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| H A D | nv50_ir_lowering_nvc0.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
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| H A D | nv50_ir_emit_nvc0.cpp | 1674 case OP_LG2:
|