| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 103 { OP_RCP, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
490 case OP_RCP:
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| H A D | nv50_ir_from_tgsi.cpp | 1519 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1536 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1595 mkOp1(OP_RCP, TYPE_F32, val, val);
1877 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2424 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
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| H A D | nv50_ir_from_sm4.cpp | 458 case SM4_OPCODE_RCP: return OP_RCP;
1509 mkOp1(OP_RCP, TYPE_F32, dst0[c], dst0[c]);
1611 mkOp1(OP_RCP, TYPE_F32, val, val);
2282 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
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| H A D | nv50_ir_peephole.cpp | 530 case OP_RCP: res.data.f32 = 1.0f / imm.reg.data.f32; break;
810 case OP_RCP:
1086 if (si && si->op == OP_RCP) {
1224 case OP_RCP:
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| H A D | nv50_ir_lowering_nv50.cpp | 414 bf = bld.mkOp1v(OP_RCP, TYPE_F32, bld.getSSA(), bf);
954 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
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| H A D | nv50_ir_emit_nv50.cpp | 1243 assert(i->op == OP_RCP);
1624 case OP_RCP:
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| H A D | nv50_ir.h | 80 OP_RCP, enumerator in enum:nv50_ir::operation
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 242 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
601 case OP_RCP:
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| H A D | nv50_ir_lowering_nvc0.cpp | 109 case OP_RCP:
939 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
951 bld.mkOp1(OP_RCP, TYPE_F32, value, i->getSrc(1));
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| H A D | nv50_ir_emit_nvc0.cpp | 1671 case OP_RCP:
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 103 { OP_RCP, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
490 case OP_RCP:
|
| H A D | nv50_ir_from_tgsi.cpp | 1519 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1536 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1595 mkOp1(OP_RCP, TYPE_F32, val, val);
1877 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2424 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
|
| H A D | nv50_ir_from_sm4.cpp | 458 case SM4_OPCODE_RCP: return OP_RCP;
1509 mkOp1(OP_RCP, TYPE_F32, dst0[c], dst0[c]);
1611 mkOp1(OP_RCP, TYPE_F32, val, val);
2282 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
|
| H A D | nv50_ir_peephole.cpp | 530 case OP_RCP: res.data.f32 = 1.0f / imm.reg.data.f32; break;
810 case OP_RCP:
1086 if (si && si->op == OP_RCP) {
1224 case OP_RCP:
|
| H A D | nv50_ir_lowering_nv50.cpp | 414 bf = bld.mkOp1v(OP_RCP, TYPE_F32, bld.getSSA(), bf);
954 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
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| H A D | nv50_ir_emit_nv50.cpp | 1243 assert(i->op == OP_RCP);
1624 case OP_RCP:
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| H A D | nv50_ir.h | 80 OP_RCP, enumerator in enum:nv50_ir::operation
|
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 242 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
601 case OP_RCP:
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| H A D | nv50_ir_lowering_nvc0.cpp | 109 case OP_RCP:
939 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
951 bld.mkOp1(OP_RCP, TYPE_F32, value, i->getSrc(1));
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| H A D | nv50_ir_emit_nvc0.cpp | 1671 case OP_RCP:
|