Searched refs:OP_SET_OR (Results 1 - 10 of 10) sorted by relevance
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 388 case OP_SET_OR:
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| H A D | nv50_ir.h | 75 OP_SET_OR, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_peephole.cpp | 1138 logop->op == OP_XOR ? OP_SET_XOR : OP_SET_OR);
1143 set0->op != OP_SET_OR &&
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 249 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
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| H A D | nv50_ir_emit_nvc0.cpp | 885 case OP_SET_OR: hi = 0x10200000; break;
1645 case OP_SET_OR:
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_target_nv50.cpp | 388 case OP_SET_OR:
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| H A D | nv50_ir.h | 75 OP_SET_OR, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_peephole.cpp | 1138 logop->op == OP_XOR ? OP_SET_XOR : OP_SET_OR);
1143 set0->op != OP_SET_OR &&
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| H A D | nv50_ir_target_nvc0.cpp | 249 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
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| H A D | nv50_ir_emit_nvc0.cpp | 885 case OP_SET_OR: hi = 0x10200000; break;
1645 case OP_SET_OR:
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Completed in 139 milliseconds