| /external/pcre/dist/sljit/ |
| H A D | sljitNativeMIPS_64.c | 38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
45 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar));
89 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar));
118 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
234 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_INT_OP) ? 32 : 64), UNMOVABLE_INS));
257 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
293 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
415 EMIT_LOGICAL(ORI, O
[all...] |
| H A D | sljitNativePPC_64.c | 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32)));
89 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2);
96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS;
107 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48)));
113 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32)));
116 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm));
312 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
320 FAIL_IF(push_inst(compiler, ORI |
[all...] |
| H A D | sljitNativePPC_32.c | 35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
185 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)));
250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value));
|
| H A D | sljitNativeMIPS_32.c | 32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
142 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS));
165 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
201 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
320 EMIT_LOGICAL(ORI, OR);
347 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst));
|
| H A D | sljitNativeTILEGX_64.c | 426 #define ORI(dst, srca, imm) \ macro
1718 FAIL_IF(ORI(ULESS_FLAG ,reg_map[src1], src2));
1780 FAIL_IF(ORI(TMP_EREG1, reg_map[src1], src2));
|
| H A D | sljitNativeMIPS_common.c | 159 #define ORI (HI(13)) macro
|
| H A D | sljitNativePPC_common.c | 195 #define ORI (HI(24)) macro
|
| /external/valgrind/main/none/tests/mips64/ |
| H A D | logical_instructions.c | 7 OR, ORI, XOR, XORI enumerator in enum:__anon33131
68 case ORI:
|
| /external/chromium_org/v8/src/mips/ |
| H A D | constants-mips.cc | 302 case ORI:
|
| H A D | assembler-mips-inl.h | 149 // For an instruction like LUI/ORI where the target bits are mixed into the
357 (instr1 & kOpcodeMask) == ORI &&
|
| H A D | assembler-mips.cc | 582 return opcode == ORI;
1576 GenInstrImmediate(ORI, rs, rt, j);
2560 if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) {
2599 CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI));
2606 *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
2665 // JALR rs reg is the rt reg specified in the ORI instruction.
2677 // JR 'rs' reg is the 'rt' reg specified in the ORI instruction (instr2).
2707 DCHECK(GetOpcodeField(instr2) == ORI);
2715 DCHECK(GetOpcodeField(instr2) == ORI);
|
| H A D | constants-mips.h | 329 ORI = ((1 << 3) + 5) << kOpcodeShift,
|
| H A D | simulator-mips.cc | 2835 case ORI:
2957 case ORI:
|
| H A D | macro-assembler-mips.cc | 5570 scratch, Operand(ORI));
5598 scratch, Operand(ORI));
|
| /external/chromium_org/v8/src/mips64/ |
| H A D | constants-mips64.cc | 320 case ORI:
|
| H A D | assembler-mips64-inl.h | 141 // For an instruction like LUI/ORI where the target bits are mixed into the
354 (instr1 & kOpcodeMask) == ORI &&
356 (instr3 & kOpcodeMask) == ORI &&
|
| H A D | assembler-mips64.cc | 554 return opcode == ORI;
1640 GenInstrImmediate(ORI, rs, rt, j);
2806 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) &&
2807 (GetOpcodeField(instr3) == ORI)) {
2862 CHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI &&
2863 GetOpcodeField(instr3) == ORI));
2872 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift)
2874 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
2896 DCHECK(GetOpcodeField(instr2) == ORI);
2904 DCHECK(GetOpcodeField(instr2) == ORI);
[all...] |
| H A D | constants-mips64.h | 294 ORI = ((1 << 3) + 5) << kOpcodeShift,
|
| H A D | macro-assembler-mips64.cc | 5524 scratch, Operand(ORI));
5536 scratch, Operand(ORI));
5566 scratch, Operand(ORI));
5579 scratch, Operand(ORI));
|
| H A D | simulator-mips64.cc | 2971 case ORI:
3107 case ORI:
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 254 // transform this into the appropriate ORI instruction.
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
566 : PPC::ORI );
863 : PPC::ORI );
1478 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
|
| H A D | PPCFastISel.cpp | 1142 Opc = PPC::ORI;
1940 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
|
| H A D | PPCRegisterInfo.cpp | 806 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
|
| /external/chromium_org/third_party/icu/source/common/ |
| H A D | ucnvisci.c | 92 ORI = 0x47, enumerator in enum:__anon11988
145 { ORIYA, ORI_MASK, ORI },
273 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
|
| /external/icu/icu4c/source/common/ |
| H A D | ucnvisci.c | 92 ORI = 0x47, enumerator in enum:__anon21776
145 { ORIYA, ORI_MASK, ORI },
273 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
|