Searched refs:Op3 (Results 1 - 17 of 17) sorted by relevance

/external/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h32 SDValue Op3, unsigned Align, bool isVolatile,
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp273 unsigned &Op3) {
283 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
552 unsigned Op1, Op2, Op3; local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
565 unsigned Op1, Op2, Op3; local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
570 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
578 unsigned Op1, Op2, Op3; local
579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument
591 unsigned Op1, Op2, Op3; local
604 unsigned Op1, Op2, Op3; local
618 unsigned Op1, Op2, Op3; local
633 unsigned Op1, Op2, Op3; local
647 unsigned Op1, Op2, Op3; local
661 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
695 unsigned Op1, Op2, Op3, Op4, Op5; local
715 unsigned Op1, Op2, Op3; local
734 unsigned Op1, Op2, Op3; local
[all...]
/external/llvm/include/llvm/Target/
H A DTargetSelectionDAGInfo.h60 SDValue Op3, unsigned Align, bool isVolatile,
77 SDValue Op3, unsigned Align, bool isVolatile,
93 SDValue Op3, unsigned Align, bool isVolatile,
107 SDValue Op3, MachinePointerInfo Op1PtrInfo,
57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h55 SDValue Op3, unsigned Align,
/external/llvm/lib/Target/X86/
H A DX86CodeEmitter.cpp452 const MachineOperand &Op3 = MI.getOperand(Op+3);
457 if (Op3.isGlobal()) {
458 DispForReloc = &Op3;
459 } else if (Op3.isSymbol()) {
460 DispForReloc = &Op3;
461 } else if (Op3.isCPI()) {
463 DispForReloc = &Op3;
465 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
466 DispVal += Op3.getOffset();
468 } else if (Op3
[all...]
H A DX86ISelDAGToDAG.cpp2763 SDValue Op0, Op1, Op2, Op3, Op4; local
2769 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2777 OutOps.push_back(Op3);
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp73 const MCOperand &Op3 = MI->getOperand(3); local
77 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
80 switch (Op3.getImm()) {
113 if (Op2.isImm() && Op3.isImm()) {
117 int64_t imms = Op3.getImm();
147 if (Op2.getImm() > Op3.getImm()) {
150 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
158 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h857 SDValue Op3);
859 SDValue Op3, SDValue Op4);
861 SDValue Op3, SDValue Op4, SDValue Op5);
873 SDValue Op1, SDValue Op2, SDValue Op3);
888 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
890 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
911 SDValue Op1, SDValue Op2, SDValue Op3);
920 SDValue Op1, SDValue Op2, SDValue Op3);
927 SDValue Op3);
H A DSelectionDAGNodes.h800 const SDValue &Op2, const SDValue &Op3) {
808 Ops[3].setInitial(Op3);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3590 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
3591 if (Op2.isReg() && Op3.isImm()) {
3592 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm());
3612 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext()));
3613 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(),
3614 Op3.getEndLoc(), getContext());
3622 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
3625 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) {
3626 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3
3687 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp93 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
91 FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp5263 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { argument
5264 SDValue Ops[] = { Op1, Op2, Op3 };
5270 SDValue Op3, SDValue Op4) {
5271 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
5277 SDValue Op3, SDValue Op4, SDValue Op5) {
5278 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
5357 SDValue Op2, SDValue Op3) {
5359 SDValue Ops[] = { Op1, Op2, Op3 };
5414 SDValue Op3) {
5416 SDValue Ops[] = { Op1, Op2, Op3 };
5269 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument
5276 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument
5355 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5411 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5420 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
5574 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5611 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5637 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
[all...]
H A DSelectionDAGBuilder.cpp4689 SDValue Op3 = getValue(I.getArgOperand(2));
4694 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4707 SDValue Op3 = getValue(I.getArgOperand(2));
4712 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4726 SDValue Op3 = getValue(I.getArgOperand(2));
4731 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
H A DLegalizeIntegerTypes.cpp221 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); local
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
/external/llvm/include/llvm/IR/
H A DPatternMatch.h1197 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument
1198 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
/external/llvm/lib/Analysis/
H A DConstantFolding.cpp1714 if (const ConstantFP *Op3 = dyn_cast<ConstantFP>(Operands[2])) {
1721 Op3->getValueAPF(),
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5552 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); local
5553 if (Op3.isMem()) {

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