Searched refs:Op5 (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp661 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
666 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
673 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
695 unsigned Op1, Op2, Op3, Op4, Op5; local
700 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
708 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h861 SDValue Op3, SDValue Op4, SDValue Op5);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp5277 SDValue Op3, SDValue Op4, SDValue Op5) {
5278 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
5276 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument

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