/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O); 43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O); 44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O); 46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, 48 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, 51 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 52 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, [all...] |
H A D | ARMInstPrinter.cpp | 339 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, argument 341 const MCOperand &MO1 = MI->getOperand(OpNum); 372 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 374 const MCOperand &MO1 = MI->getOperand(OpNum); 375 const MCOperand &MO2 = MI->getOperand(OpNum+1); 376 const MCOperand &MO3 = MI->getOperand(OpNum+2); 391 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 393 const MCOperand &MO1 = MI->getOperand(OpNum); 394 const MCOperand &MO2 = MI->getOperand(OpNum+1); 481 unsigned OpNum, [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.h | 46 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O); 47 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 48 void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 49 void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 50 void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 51 void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 52 void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 53 void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 54 void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 55 void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostrea [all...] |
H A D | SystemZInstPrinter.cpp | 54 void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, argument 56 int64_t Value = MI->getOperand(OpNum).getImm(); 61 void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, argument 63 int64_t Value = MI->getOperand(OpNum).getImm(); 68 void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum, argument 70 int64_t Value = MI->getOperand(OpNum).getImm(); 75 void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum, argument 77 int64_t Value = MI->getOperand(OpNum).getImm(); 82 void SystemZInstPrinter::printS16ImmOperand(const MCInst *MI, int OpNum, argument 84 int64_t Value = MI->getOperand(OpNum) 89 printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 96 printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 103 printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 110 printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 156 printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 59 void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O); 60 void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O); 61 void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O); 62 void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O); 63 void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O); 64 void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O); 65 void printArithExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O); 67 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, 70 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) { argument 71 printMemExtend(MI, OpNum, 83 printUImm12Offset(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 88 printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument [all...] |
H A D | AArch64InstPrinter.cpp | 640 int OpNum = LdStDesc->ListOperand; local 641 printVectorList(MI, OpNum++, O, ""); 644 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; 647 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); 652 unsigned Reg = MI->getOperand(OpNum++).getReg(); 939 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, argument 941 const MCOperand &MO = MI->getOperand(OpNum); 946 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); 949 printShifter(MI, OpNum + 1, O); 956 printShifter(MI, OpNum 960 printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 967 printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 974 printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 985 printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 991 printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 997 printArithExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1023 printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width) argument 1040 printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1046 printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1052 printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1058 printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1063 printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O) argument 1074 printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O) argument 1087 printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1098 printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1153 printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O, StringRef LayoutSuffix) argument 1196 printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1203 printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1214 printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1219 printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1243 printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 58 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 61 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 64 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 67 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 70 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 74 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at 78 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, 82 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, argument 85 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); 87 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, argument 128 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 138 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 148 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 159 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 171 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 182 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset) const argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 49 void printOperand(const MachineInstr *MI, int OpNum, 51 void printSrcMemOperand(const MachineInstr *MI, int OpNum, 64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument 66 const MachineOperand &MO = MI->getOperand(OpNum); 105 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument 107 const MachineOperand &Base = MI->getOperand(OpNum); 108 const MachineOperand &Disp = MI->getOperand(OpNum+1); 115 printOperand(MI, OpNum+1, O, "nohash"); 120 printOperand(MI, OpNum, O);
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.h | 39 void printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, 41 void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, 43 void printLdStCode(const MCInst *MI, int OpNum, 45 void printMemOperand(const MCInst *MI, int OpNum, 47 void printProtoIdent(const MCInst *MI, int OpNum,
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H A D | NVPTXInstPrinter.cpp | 96 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, argument 98 const MCOperand &MO = MI->getOperand(OpNum); 146 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, argument 148 const MCOperand &MO = MI->getOperand(OpNum); 219 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum, argument 222 const MCOperand &MO = MI->getOperand(OpNum); 267 void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum, argument 269 printOperand(MI, OpNum, O); 273 printOperand(MI, OpNum + 1, O); 275 if (MI->getOperand(OpNum 283 printProtoIdent(const MCInst *MI, int OpNum, raw_ostream &O, const char *Modifier) argument [all...] |
/external/llvm/include/llvm/MC/MCParser/ |
H A D | MCParsedAsmOperand.h | 37 void setMCOperandNum (unsigned OpNum) { MCOperandNum = OpNum; } argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMAsmPrinter.h | 59 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, 62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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H A D | ARMAsmPrinter.cpp | 126 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument 128 const MachineOperand &MO = MI->getOperand(OpNum); 201 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument 211 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O); 213 if (MI->getOperand(OpNum).isReg()) { 215 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) 221 if (!MI->getOperand(OpNum).isImm()) 223 O << MI->getOperand(OpNum).getImm(); 227 printOperand(MI, OpNum, O); 230 if (MI->getOperand(OpNum) 376 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 899 int OpNum = 1; local 950 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; local [all...] |
H A D | Thumb2SizeReduction.cpp | 376 unsigned OpNum = 3; // First 'rest' of operands. local 414 OpNum = 4; 435 OpNum = 0; 444 OpNum = 2; 452 OpNum = 0; 459 OpNum = 2; 509 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) 510 MIB.addOperand(MI->getOperand(OpNum));
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/external/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 2363 unsigned OpNum = 0; local 2365 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) || 2366 popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS) || 2367 OpNum+1 > Record.size()) 2370 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType()); 2375 if (OpNum < Record.size()) { 2380 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP)) 2382 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP)) 2388 if (Record[OpNum] & (1 << bitc::PEO_EXACT)) 2392 if (0 != (Record[OpNum] 2410 unsigned OpNum = 0; local 2434 unsigned OpNum = 0; local 2456 unsigned OpNum = 0; local 2477 unsigned OpNum = 0; local 2502 unsigned OpNum = 0; local 2517 unsigned OpNum = 0; local 2542 unsigned OpNum = 0; local 2553 unsigned OpNum = 0; local 2566 unsigned OpNum = 0; local 2586 unsigned OpNum = 0; local 2610 unsigned OpNum = 0; local 2762 unsigned OpNum = 4; local 2900 unsigned OpNum = 0; local 2912 unsigned OpNum = 0; local 2933 unsigned OpNum = 0; local 2947 unsigned OpNum = 0; local 2971 unsigned OpNum = 0; local 3011 unsigned OpNum = 0; local 3051 unsigned OpNum = 2; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 93 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O); 99 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 102 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, 209 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum, argument 211 const MachineOperand &MO = MI->getOperand(OpNum); 265 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument 268 const MachineOperand &MO = MI->getOperand(OpNum); 271 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O)) 291 printOperand(MI, OpNum, O); 321 printOperand(MI, OpNum, 345 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 156 int getOperandConstraint(unsigned OpNum, argument 158 if (OpNum < NumOperands && 159 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 161 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreAsmPrinter.cpp | 75 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, 256 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, argument 262 printOperand(MI, OpNum, O); 264 printOperand(MI, OpNum + 1, O);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 438 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument 445 const MachineOperand &MO = MI->getOperand(OpNum); 449 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O); 485 if (OpNum == 0) 487 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 503 unsigned RegOp = OpNum; 509 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; 512 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum 539 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
H A D | MipsAsmPrinter.h | 124 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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/external/llvm/utils/PerfectShuffle/ |
H A D | PerfectShuffle.cpp | 106 unsigned short OpNum; member in struct:Operator 112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) { 394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0; 395 assert(OpNum < 16 && "Too few bits to encode operation!"); 402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS;
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 396 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 398 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 400 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 405 unsigned OpNum,
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/external/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 75 unsigned short LastOpNum; // OpNum on LastUse. 190 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, 192 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum, 195 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 583 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, argument 608 LRI->LastOpNum = OpNum; 616 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, argument 623 MachineOperand &MO = MI->getOperand(OpNum); 659 LRI->LastOpNum = OpNum; 664 // setPhysReg - Change operand OpNum i 667 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 61 /// class constraint for OpNum, or NULL. 63 unsigned OpNum, 963 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 981 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument 999 /// does not take an operand index. Instead sets \p OpNum to the index of the 1001 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, argument 1008 /// before MI to eliminate an unwanted dependency on OpNum. 1025 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
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/external/llvm/lib/Target/R600/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 42 static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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