Searched refs:Opc (Results 1 - 25 of 154) sorted by relevance

1234567

/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp45 unsigned Opc = MI->getOpcode(); local
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
68 unsigned Opc = MI->getOpcode(); local
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc
86 unsigned Opc = 0, ZeroReg = 0; local
191 unsigned Opc = 0; local
232 unsigned Opc = 0; local
269 unsigned Opc; local
442 compareOpndSize(unsigned Opc, const MachineFunction &MF) const argument
[all...]
H A DMips16InstrInfo.cpp68 unsigned Opc = 0; local
72 Opc = Mips::MoveR3216;
75 Opc = Mips::Move32R16;
78 Opc = Mips::Mfhi16, SrcReg = 0;
82 Opc = Mips::Mflo16, SrcReg = 0;
85 assert(Opc && "Cannot copy registers");
87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
104 unsigned Opc = 0; local
106 Opc = Mips::SwRxSpImmX16;
107 assert(Opc
120 unsigned Opc = 0; local
206 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; local
236 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? local
[all...]
H A DMipsFastISel.cpp97 MachineInstrBuilder EmitInst(unsigned Opc) { argument
98 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
101 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) { argument
102 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
106 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg, argument
108 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
111 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg, argument
113 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
160 unsigned Opc; local
164 Opc
219 unsigned Opc; local
375 unsigned Opc = Mips::ADDiu; local
[all...]
H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMipsSEInstrInfo.h68 unsigned getOppositeBranchOpc(unsigned Opc) const override;
82 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
86 std::pair<bool, bool> compareOpndSize(unsigned Opc,
H A DMips16InstrInfo.h67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
109 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
112 unsigned Opc) const;
H A DMipsInstrInfo.h85 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
132 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
134 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
H A DMips16ISelDAGToDAG.h26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc DL,
H A DMipsAnalyzeImmediate.cpp15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
100 Seq[0].Opc = LUi;
H A DMips16ISelDAGToDAG.cpp46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, argument
49 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
259 unsigned Opc = InFlag.getOpcode(); (void)Opc; local
260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
261 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
348 bool isUncondBranchOpcode(int Opc) { argument
349 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
353 bool isCondBranchOpcode(int Opc) { argument
354 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
358 isJumpTableBranchOpcode(int Opc) argument
364 isIndirectBranchOpcode(int Opc) argument
368 isPopOpcode(int Opc) argument
374 isPushOpcode(int Opc) argument
[all...]
H A DARMInstrInfo.h31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
H A DARMInstrInfo.cpp53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54 switch (Opc) {
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? variable
129 TII.get(Opc), TempReg)
131 if (Opc == ARM::LDRcp)
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
142 if (Opc == ARM::PICADD)
H A DThumb1InstrInfo.h31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
H A DARMFastISel.cpp476 unsigned Opc; local
479 Opc = ARM::FCONSTD;
482 Opc = ARM::FCONSTS;
486 TII.get(Opc), DestReg).addImm(Imm));
501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; local
505 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
520 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; local
525 TII.get(Opc), ImmReg)
536 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; local
539 TII.get(Opc), ImmRe
595 unsigned Opc; local
633 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; local
649 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; local
714 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; local
892 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; local
960 unsigned Opc; local
1092 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; local
1351 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; local
1580 unsigned Opc; local
1604 unsigned Opc; local
1758 unsigned Opc; local
1804 unsigned Opc; local
2620 uint32_t Opc : 16; member in struct:InstructionTable
2679 unsigned Opc = ITP->Opc; local
2764 unsigned Opc = ARM::MOVsr; local
2884 uint16_t Opc[2]; // ARM, Thumb. member in struct:__anon25973::FoldableLoadExtendsStruct
2947 unsigned Opc; local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { argument
62 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
63 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
67 static bool IsUnconditionalJump(int Opc) { argument
68 return (Opc == Hexagon::JMP);
114 int Opc = MI->getOpcode(); local
115 if (IsConditionalBranch(Opc)) {
H A DHexagonSplitConst32AndConst64.cpp87 int Opc = MI->getOpcode(); local
88 if (Opc == Hexagon::CONST32_set) {
101 else if (Opc == Hexagon::CONST32_set_jt) {
114 else if (Opc == Hexagon::CONST32_Label) {
127 else if (Opc == Hexagon::CONST32_Int_Real) {
138 else if (Opc == Hexagon::CONST64_Int_Real) {
/external/llvm/include/llvm/IR/
H A DAutoUpgrade.h55 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
61 Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp108 unsigned Opc = MBBI->getOpcode(); local
109 switch (Opc) {
155 unsigned Opc;
157 Opc = getLEArOpcode(IsLP64);
159 Opc = isSub
174 Opc = isSub
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
212 unsigned Opc
[all...]
H A DX86FastISel.cpp92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
367 unsigned Opc = 0; local
373 Opc = X86::MOV8rm;
377 Opc = X86::MOV16rm;
381 Opc = X86::MOV32rm;
386 Opc = X86::MOV64rm;
391 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
394 Opc = X86::LD_Fp32m;
400 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
403 Opc
429 unsigned Opc = 0; local
495 unsigned Opc = 0; local
532 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
593 unsigned Opc = 0; local
1264 unsigned Opc = X86::getSETFromCond(CC); local
1842 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); local
1897 unsigned *Opc = nullptr; local
1938 unsigned Opc; local
2192 unsigned Opc; local
2331 unsigned Opc; local
2507 unsigned Opc; local
3089 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; local
3175 unsigned Opc = 0; local
3293 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; local
3307 unsigned Opc = 0; local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
430 unsigned Opc; local
454 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
457 Opc = (IsZExt ?
462 Opc = (IsZExt ?
465 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
469 Opc = PPC::LD;
475 Opc = PPC::LFS;
478 Opc
570 unsigned Opc; local
971 unsigned Opc; local
1064 unsigned Opc; local
1106 unsigned Opc; local
1633 unsigned Opc; local
1830 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; local
2031 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; local
2180 FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp344 unsigned Opc; local
348 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
352 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
356 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
360 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
364 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
369 unsigned Opc; local
373 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
377 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
381 Opc
2399 unsigned Opc = 0; local
2787 unsigned Opc = 0; local
2931 unsigned Opc = 0; local
3442 unsigned Opc; local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp580 unsigned Opc = 0; local
584 Opc = AArch64::SUBSWri;
588 Opc = AArch64::SUBSXri;
593 const MCInstrDesc &MCID = TII->get(Opc);
612 unsigned Opc = 0; local
618 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
619 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
620 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
621 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
622 case AArch64::ADDSWri: Opc
[all...]
H A DAArch64InstrInfo.h208 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } argument
210 static inline bool isCondBranchOpcode(int Opc) { argument
211 switch (Opc) {
227 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } argument
/external/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp420 void SingletonExists(unsigned Opc) const;
438 unsigned Opc) const;
440 bool doesOpcodeNeedPredicate(unsigned Opc) const;
443 unsigned Opc) const;
446 unsigned Opc) const;
450 unsigned Opc) const;
459 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const;
460 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const;
818 unsigned Opc = decodeULEB128(Buffer);
830 << NumberedInstructions->at(Opc)
[all...]

Completed in 4600 milliseconds

1234567