/external/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 75 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 77 << " to " << PrintReg(PhysReg, TRI) << ':'); 79 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 80 MRI->setPhysRegUsed(PhysReg); 81 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 90 unsigned PhysReg = VRM->getPhys(VirtReg.reg); local 92 << " from " << PrintReg(PhysReg, TRI) << ':'); 94 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 103 unsigned PhysReg) { 114 // The BitVector is indexed by PhysReg, no 102 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 120 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 141 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here. member in struct:__anon25790::RAFast::LiveReg 79 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} 125 void markRegUsedInInstr(unsigned PhysReg) { argument 126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 131 bool isRegUsedInInstr(unsigned PhysReg) const { 132 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 178 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 179 unsigned calcSpillCost(unsigned PhysReg) const; 180 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg); 187 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg); 346 unsigned PhysReg = MO.getReg(); local 400 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument 491 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument 500 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 540 unsigned PhysReg = *I; local 667 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument 741 unsigned PhysReg = LRI->PhysReg; local 764 unsigned PhysReg = LRI->PhysReg; local 969 unsigned PhysReg = LRI->PhysReg; local 1025 unsigned PhysReg = LRI->PhysReg; local [all...] |
H A D | RegisterClassInfo.cpp | 98 unsigned PhysReg = RawOrder[i]; local 100 if (Reserved.test(PhysReg)) 102 unsigned Cost = TRI->getCostPerUse(PhysReg); 105 if (CSRNum[PhysReg]) 106 // PhysReg aliases a CSR, save it for later. 107 CSRAlias.push_back(PhysReg); 111 RCI.Order[N++] = PhysReg; 120 unsigned PhysReg = CSRAlias[i]; local 121 unsigned Cost = TRI->getCostPerUse(PhysReg); 124 RCI.Order[N++] = PhysReg; [all...] |
H A D | AllocationOrder.h | 79 /// Return true if PhysReg is a preferred register. 80 bool isHint(unsigned PhysReg) const { 81 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
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H A D | InterferenceCache.h | 39 /// of PhysReg in all basic blocks. 41 /// PhysReg - The register currently represented. 42 unsigned PhysReg; member in class:llvm::InterferenceCache::Entry 63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg. 86 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have 97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {} 101 PhysReg = 0; 107 unsigned getPhysReg() const { return PhysReg; } 148 // get - Get a valid entry for PhysReg. 149 Entry *get(unsigned PhysReg); 202 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument [all...] |
H A D | RegAllocGreedy.cpp | 248 unsigned PhysReg; member in struct:__anon25792::RAGreedy::GlobalSplitCandidate 253 // Interference for PhysReg. 261 PhysReg = Reg; 281 /// Candidate info for each PhysReg in AllocationOrder. 338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, 365 unsigned PhysReg, unsigned &CostPerUseLimit, 572 unsigned PhysReg; local 573 while ((PhysReg = Order.next())) 574 if (!Matrix->checkInterference(VirtReg, PhysReg)) 614 unsigned PhysReg; local 675 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 757 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument 1582 calcGapWeights(unsigned PhysReg, SmallVectorImpl<float> &GapWeight) argument [all...] |
H A D | InterferenceCache.cpp | 55 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument 56 unsigned E = PhysRegEntries[PhysReg]; 57 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 73 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 74 PhysRegEntries[PhysReg] = E; 88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 99 PhysReg = physReg; 105 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 114 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 185 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { [all...] |
H A D | RegAllocBasic.cpp | 112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 164 // Spill or split all live virtual registers currently unified under PhysReg 167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 190 // Spill each interfering vreg allocated to PhysReg or an alias. 228 while (unsigned PhysReg = Order.next()) { 229 // Check for interference in PhysReg 230 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 232 // PhysReg i [all...] |
H A D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | VirtRegMap.cpp | 250 // assigned PhysReg must be marked as live-in to those blocks. 251 unsigned PhysReg = VRM->getPhys(VirtReg); local 252 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); 260 if (!LiveIn[i]->isLiveIn(PhysReg)) 261 LiveIn[i]->addLiveIn(PhysReg); 327 // If we encounter a VirtReg or PhysReg then get at the PhysReg and add 339 unsigned PhysReg = VRM->getPhys(VirtReg); local 340 assert(PhysReg != VirtRegMap::NO_PHYS_REG && 342 assert(!MRI->isReserved(PhysReg) [all...] |
H A D | LiveRangeCalc.h | 113 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 115 SlotIndex Kill, unsigned PhysReg); 162 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 163 void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0);
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H A D | LiveRangeCalc.cpp | 134 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) { argument 150 if (findReachingDefs(LR, *KillMBB, Kill, PhysReg)) 170 SlotIndex Kill, unsigned PhysReg) { 190 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && 191 !MBB->isLiveIn(PhysReg)) { 169 findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, SlotIndex Kill, unsigned PhysReg) argument
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H A D | MachineRegisterInfo.cpp | 406 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, argument 408 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 412 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
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H A D | MachineBasicBlock.cpp | 352 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument 354 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); 359 bool LiveIn = isLiveIn(PhysReg); 367 if (I->getOperand(1).getReg() == PhysReg) { 377 .addReg(PhysReg, RegState::Kill); 379 addLiveIn(PhysReg);
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveRegMatrix.h | 86 /// assigned to PhysReg or its aliases. This interference could be resolved 96 /// regmask operand that doesn't preserve PhysReg. This typically means 97 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 101 /// Check for interference before assigning VirtReg to PhysReg. 102 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 107 /// Assign VirtReg to PhysReg. 109 /// update VirtRegMap. The live range is expected to be available in PhysReg. 110 void assign(LiveInterval &VirtReg, unsigned PhysReg); 112 /// Unassign VirtReg from its PhysReg [all...] |
H A D | RegisterClassInfo.h | 108 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. 109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 111 if (unsigned N = CSRNum[PhysReg])
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H A D | MachineOperand.h | 467 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 471 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { argument 473 assert(PhysReg < (1u << 30) && "Not a physical register"); 474 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 477 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 478 bool clobbersPhysReg(unsigned PhysReg) const { 479 return clobbersPhysReg(getRegMask(), PhysReg);
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H A D | MachineRegisterInfo.h | 540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 696 /// canReserveReg - Returns true if PhysReg can be used as a reserved 699 bool canReserveReg(unsigned PhysReg) const { 700 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 713 /// isReserved - Returns true when PhysReg is a reserved register. 718 bool isReserved(unsigned PhysReg) const { 719 return getReservedRegs().test(PhysReg); 722 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 728 bool isAllocatable(unsigned PhysReg) cons [all...] |
H A D | MachineBasicBlock.h | 322 /// Add PhysReg as live in to this block, and ensure that there is a copy of 323 /// PhysReg to a virtual register of class RC. Return the virtual register 324 /// that is a copy of the live in PhysReg. 325 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 407 std::string PhysReg; 410 return PhysReg; 414 return PhysReg; 416 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) 418 PhysReg += "::"; 419 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 420 return PhysReg; 523 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 524 if (PhysReg.empty()) { 534 PhysRegInputs->push_back(PhysReg); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 114 unsigned &PhysReg, int &Cost) { 127 PhysReg = Reg; 474 unsigned PhysReg = 0; 477 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 478 assert((PhysReg == 0 || !isChain) && 486 PhysReg = 0; 495 : SDep(OpSU, SDep::Data, PhysReg); 111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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H A D | FunctionLoweringInfo.cpp | 129 std::pair<unsigned, const TargetRegisterClass*> PhysReg = local 132 if (PhysReg.first == SP)
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H A D | SelectionDAGBuilder.cpp | 6122 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 6132 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 6136 MVT RegVT = *PhysReg.second->vt_begin(); 6161 if (unsigned AssignedReg = PhysReg.first) { 6162 const TargetRegisterClass *RC = PhysReg.second; 6194 if (const TargetRegisterClass *RC = PhysReg.second) {
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 373 struct PhysRegOp PhysReg; member in union:__anon26038::MipsOperand::__anon26039 696 return PhysReg.Num; 880 OS << "PhysReg<" << PhysReg.Num << ">";
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