Searched refs:RA (Results 1 - 25 of 51) sorted by relevance

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/external/valgrind/main/none/tests/ppc32/
H A Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, R
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H A Ddata-cache-instructions.c50 asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr));
/external/valgrind/main/none/tests/ppc64/
H A Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, R
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H A Ddata-cache-instructions.c50 asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr));
/external/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
326 // CHECK-NEXT: 1 | struct RA (bas
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H A Dms-x86-pack-and-align.cpp430 struct RA {}; struct
441 struct __declspec(align(8)) RB2 : virtual RA {
445 struct __declspec(align(8)) RB3 : virtual RA {
476 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty)
484 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty)
519 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty)
527 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
/external/qemu/disas/
H A Dppc.c688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
685 #define RA macro
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/external/smack/src/org/xbill/DNS/
H A DFlags.java29 public static final byte RA = 8; field in class:Flags
49 flags.add(RA, "ra");
/external/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp164 struct RA { struct in namespace:Test9
169 struct RC final : public RA {
185 return static_cast<RA*>(x)->f();
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp46 const MCReadAdvanceEntry *RA,
56 ReadAdvanceTable = RA;
40 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp153 void MarkValue(const RetOrArg &RA, Liveness L,
155 void MarkLive(const RetOrArg &RA);
157 void PropagateLiveness(const RetOrArg &RA);
619 /// MarkValue - This function marks the liveness of RA depending on L. If L is
621 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
623 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
626 case Live: MarkLive(RA); break;
633 Uses.insert(std::make_pair(*UI, RA));
658 void DAE::MarkLive(const RetOrArg &RA) { argument
659 if (LiveFunctions.count(RA
671 PropagateLiveness(const RetOrArg &RA) argument
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H A DMergeFunctions.cpp450 Attribute RA = *RI; local
451 if (LA < RA)
453 if (RA < LA)
553 const ConstantArray *RA = cast<ConstantArray>(R); local
560 cast<Constant>(RA->getOperand(i))))
/external/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp467 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
1395 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit,
1397 if (RA == ATTR_MIXED && AllowMixed)
1399 else if (RA == ATTR_ALL_SET && !AllowMixed)
1517 bitAttr_t RA = ATTR_NONE;
1525 switch (RA) {
1532 RA = ATTR_ALL_SET;
1538 RA = ATTR_MIXED;
1547 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1548 RA
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/external/libpcap/
H A Dtokdefs.h90 RA = 308, enumerator in enum:yytokentype
211 #define RA 308 macro
/external/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h53 const MCReadAdvanceEntry *RA,
H A DMCRegisterInfo.h239 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
252 RAReg = RA;
/external/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
193 // Reserve RA if in mips16 mode.
196 Reserved.set(Mips::RA);
H A DMipsLongBranch.cpp295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
326 .addReg(Mips::RA).addReg(Mips::AT);
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
H A DMips16FrameLowering.cpp112 // Registers RA, S0,S1 are the callee saved registers and they
118 // RA and return address is taken, because it has already been added in
120 // It's killed at the spill, unless the register is RA and return address
123 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
137 // Registers RA,S0,S1 are the callee saved registers and they will be restored
H A DMipsSEInstrInfo.cpp438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
600 unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA; local
612 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp55 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
58 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp247 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local
252 InitX86MCRegisterInfo(X, RA,
255 RA);
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp507 const Argument *RA = cast<Argument>(RV); local
508 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
542 const APInt &RA = RC->getValue()->getValue(); local
543 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
546 return LA.ult(RA) ? -1 : 1;
551 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local
554 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
563 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
569 long X = compare(LA->getOperand(i), RA->getOperand(i));
3991 const SCEV *RA
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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp66 InitMipsMCRegisterInfo(X, Mips::RA);
/external/chromium_org/third_party/skia/third_party/lua/src/
H A Dlvm.c489 #define RA(i) (base+GETARG_A(i)) macro
553 ra = RA(i);
659 ra = RA(i); /* 'luav_concat' may invoke TMs and move the stack */
800 ra = RA(i);
849 ra = RA(i); /* previous call may change the stack */

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