Searched refs:RC (Results 1 - 25 of 213) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h66 // Compute all information about RC.
67 void compute(const TargetRegisterClass *RC) const;
69 // Return an up-to-date RCInfo for RC.
70 const RCInfo &get(const TargetRegisterClass *RC) const {
71 const RCInfo &RCI = RegClass[RC->getID()];
73 compute(RC);
85 /// registers in RC in the current function.
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
87 return get(RC).NumRegs;
90 /// getOrder - Returns the preferred allocation order for RC
119 getMinCost(const TargetRegisterClass *RC) argument
127 getLastCostChange(const TargetRegisterClass *RC) argument
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H A DFastISel.h259 const TargetRegisterClass *RC);
264 const TargetRegisterClass *RC,
270 const TargetRegisterClass *RC,
277 const TargetRegisterClass *RC,
285 const TargetRegisterClass *RC,
291 const TargetRegisterClass *RC,
298 const TargetRegisterClass *RC,
305 const TargetRegisterClass *RC,
313 const TargetRegisterClass *RC,
321 const TargetRegisterClass *RC,
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
30 if (RC == &NVPTX::Float32RegsRegClass) {
33 if (RC == &NVPTX::Float64RegsRegClass) {
35 } else if (RC == &NVPTX::Int64RegsRegClass) {
37 } else if (RC == &NVPTX::Int32RegsRegClass) {
39 } else if (RC == &NVPTX::Int16RegsRegClass) {
41 } else if (RC == &NVPTX::Int1RegsRegClass) {
43 } else if (RC == &NVPTX::SpecialRegsRegClass) {
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument
52 if (RC
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H A DNVPTXRegisterInfo.h67 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
68 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
/external/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC
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/external/llvm/lib/Target/R600/
H A DSIRegisterInfo.cpp35 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
37 return RC->getNumRegs();
72 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
73 if (!RC) {
76 return !hasVGPRs(RC);
79 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
80 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
81 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
82 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
83 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
108 getSubRegClass( const TargetRegisterClass *RC, unsigned SubIdx) const argument
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H A DSIRegisterInfo.h29 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
43 bool isSGPRClass(const TargetRegisterClass *RC) const;
46 bool hasVGPRs(const TargetRegisterClass *RC) const;
52 /// \returns The register class that is used for a sub-register of \p RC for
53 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
55 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
70 bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
H A DR600RegisterInfo.h41 getRegClassWeight(const TargetRegisterClass *RC) const override;
H A DSIFixSGPRCopies.cpp143 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local
144 RC = TRI->getSubRegClass(RC, SubReg);
149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
156 return RC;
165 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); local
166 return TRI->getSubRegClass(RC, SubReg);
224 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg, local
226 MRI.constrainRegClass(Reg, RC);
229 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, local
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/external/llvm/lib/CodeGen/
H A DLiveStackAnalysis.cpp59 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
65 S2RCMap.insert(std::make_pair(Slot, RC));
69 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
81 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
82 if (RC)
83 OS << " [" << RC->getName() << "]\n";
H A DRegisterClassInfo.cpp76 /// compute - Compute the preferred allocation order for RC with reserved
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 RCInfo &RCI = RegClass[RC->getID()];
83 unsigned NumRegs = RC->getNumRegs();
96 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
132 // Check if RC is a proper sub-class.
133 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
134 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
141 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
155 const TargetRegisterClass *RC local
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H A DTargetRegisterInfo.cpp87 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
88 if (!RC || RC->isAllocatable())
89 return RC;
91 const unsigned *SubClass = RC->getSubClassMask();
118 const TargetRegisterClass* RC = *I; local
119 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
120 (!BestRC || BestRC->hasSubClass(RC)))
121 BestRC = RC;
130 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument
235 const TargetRegisterClass *RC = local
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/external/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp83 const TargetRegisterClass *RC; local
85 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
87 RC = ST.isABI_N64() ?
90 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
101 const TargetRegisterClass *RC; local
102 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
103 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
109 const TargetRegisterClass *RC = ST.isABI_N64() ? local
112 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
113 RC
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H A DMipsInstrInfo.h93 const TargetRegisterClass *RC,
95 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
101 const TargetRegisterClass *RC,
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
109 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
H A DMips16RegisterInfo.h35 const TargetRegisterClass *RC,
H A DMipsSEInstrInfo.cpp185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
195 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
197 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
199 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
201 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
203 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
205 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
207 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
209 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
388 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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/external/llvm/utils/release/
H A Dtest-release.sh28 RC=""
72 -rc | --rc | -RC | --RC )
74 RC="rc$1"
77 RC=final
145 if [ -z "$RC" ]; then
169 BuildDir=$BuildDir/$RC
179 if [ $RC != "final" ]; then
180 Package=$Package-$RC
225 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC > /de
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h125 bool hasSubClass(const TargetRegisterClass *RC) const {
126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(this);
142 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
144 bool hasSuperClassEq(const TargetRegisterClass *RC) cons
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/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp53 const TargetRegisterClass *RC,
55 assert((RC == &ARM::tGPRRegClass ||
59 if (RC == &ARM::tGPRRegClass ||
81 const TargetRegisterClass *RC,
83 assert((RC == &ARM::tGPRRegClass ||
87 if (RC == &ARM::tGPRRegClass ||
51 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
79 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb1InstrInfo.h48 const TargetRegisterClass *RC,
54 const TargetRegisterClass *RC,
H A DThumb1RegisterInfo.h30 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
55 const TargetRegisterClass *RC,
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h76 getSubClassWithSubReg(const TargetRegisterClass *RC,
80 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
94 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; local
171 const CodeGenRegister::Set &Regs = RC.getMembers();
176 RC.buildRegUnitSet(RegUnits);
180 OS << "}, \t// " << RC.getName() << "\n";
183 << " return RCWeightTable[RC->getID()];\n"
285 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
291 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
854 ArrayRef<Record*> Order = RC
887 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
995 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1033 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1098 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1127 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1143 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1179 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1245 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; local
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/external/llvm/include/llvm/IR/
H A DInlineAsm.h251 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument
252 // Store RC + 1, reserve the value 0 to mean 'no register class'.
253 ++RC;
254 assert(RC <= 0x7fff && "Too large register class ID");
256 return InputFlag | (RC << 16);
289 /// class constraint. Sets RC to the register class ID.
290 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument
295 // stores RC + 1.
298 RC = High - 1;
/external/clang/lib/AST/
H A DRawCommentList.cpp213 void RawCommentList::addComment(const RawComment &RC, argument
215 if (RC.isInvalid())
221 RC.getLocStart())) {
228 if (RC.isOrdinary())
234 Comments.push_back(new (Allocator) RawComment(RC));
239 const RawComment &C2 = RC;
249 RC.isParseAllComments());
251 Comments.push_back(new (Allocator) RawComment(RC));

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