/external/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 80 RCInfo &RCI = RegClass[RC->getID()]; local 85 if (!RCI.Order) 86 RCI.Order.reset(new MCPhysReg[NumRegs]); 111 RCI.Order[N++] = PhysReg; 115 RCI.NumRegs = N + CSRAlias.size(); 116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 124 RCI.Order[N++] = PhysReg; 129 if (StressRA && RCI.NumRegs > StressRA) 130 RCI.NumRegs = StressRA; 134 if (Super != RC && getNumAllocatableRegs(Super) > RCI [all...] |
H A D | TargetRegisterInfo.cpp | 192 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 193 if (RCI.getSubReg() == Idx) 196 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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H A D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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H A D | RegisterPressure.cpp | 189 RCI = rci; 626 const RegisterClassInfo *RCI, 636 unsigned Limit = RCI->getRegPressureSetLimit(i); 768 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, 834 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); 962 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, 623 computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec, ArrayRef<unsigned> NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef<unsigned> LiveThruPressureVec) argument
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H A D | PostRASchedulerList.cpp | 192 AliasAnalysis *AA, const RegisterClassInfo &RCI, 207 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : 209 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr)); 190 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
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H A D | CriticalAntiDepBreaker.cpp | 31 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : argument 36 RegClassInfo(RCI),
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H A D | RegAllocGreedy.cpp | 113 RegisterClassInfo RCI; member in class:__anon25792::RAGreedy 1498 const RegisterClassInfo &RCI) { 1506 return RCI.getNumAllocatableRegs(ConstrainedRC); 1536 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); 1546 TRI, RCI)) { 2325 RCI.runOnMachineFunction(mf); 1495 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
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H A D | TargetLoweringBase.cpp | 988 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 989 SuperRegRC.setBitsInMask(RCI.getMask());
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H A D | AggressiveAntiDepBreaker.cpp | 118 const RegisterClassInfo &RCI, 124 RegClassInfo(RCI), 117 AggressiveAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector& CriticalPathRCs) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 71 const RCInfo &RCI = RegClass[RC->getID()]; local 72 if (Tag != RCI.Tag) 74 return RCI;
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H A D | RegisterPressure.h | 253 const RegisterClassInfo *RCI; 288 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp), 292 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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/external/llvm/lib/Transforms/Scalar/ |
H A D | ConstantHoisting.cpp | 241 for (auto const &RCI : ConstInfo.RebasedConstants) 242 for (auto const &U : RCI.Uses) 550 for (auto const &RCI : ConstInfo.RebasedConstants) { 552 for (auto const &U : RCI.Uses) 553 emitBaseConstants(Base, RCI.Offset, U);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64A57FPLoadBalancing.cpp | 113 RegisterClassInfo RCI; member in class:__anon25928::AArch64A57FPLoadBalancing 302 RCI.runOnMachineFunction(F); 490 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 2181 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2182 E = RI->regclass_end(); RCI != E; ++RCI) { 2183 const TargetRegisterClass *RC = *RCI;
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