Searched refs:Reg (Results 1 - 25 of 321) sorted by relevance

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/external/qemu/target-i386/
H A Dops_sse_header.h20 #define Reg MMXReg macro
23 #define Reg XMMReg macro
30 #define dh_ctype_Reg Reg *
37 DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) variable
38 DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) variable
39 DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg) variable
40 DEF_HELPER_3(glue(psrld, SUFFIX), void, env, Reg, Re variable
41 DEF_HELPER_3(glue(psrad, SUFFIX), void, env, Reg, Reg) variable
42 DEF_HELPER_3(glue(pslld, SUFFIX), void, env, Reg, Reg) variable
43 DEF_HELPER_3(glue(psrlq, SUFFIX), void, env, Reg, Reg) variable
44 DEF_HELPER_3(glue(psllq, SUFFIX), void, env, Reg, Reg) variable
47 DEF_HELPER_3(glue(psrldq, SUFFIX), void, env, Reg, Reg) variable
48 DEF_HELPER_3(glue(pslldq, SUFFIX), void, env, Reg, Reg) variable
112 DEF_HELPER_3(glue(pmuludq, SUFFIX), void, env, Reg, Reg) variable
113 DEF_HELPER_3(glue(pmaddwd, SUFFIX), void, env, Reg, Reg) variable
115 DEF_HELPER_3(glue(psadbw, SUFFIX), void, env, Reg, Reg) variable
116 DEF_HELPER_4(glue(maskmov, SUFFIX), void, env, Reg, Reg, tl) variable
117 DEF_HELPER_2(glue(movl_mm_T0, SUFFIX), void, Reg, i32) variable
119 DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64) variable
123 DEF_HELPER_3(glue(pshufw, SUFFIX), void, Reg, Reg, int) variable
228 DEF_HELPER_3(glue(packsswb, SUFFIX), void, env, Reg, Reg) variable
229 DEF_HELPER_3(glue(packuswb, SUFFIX), void, env, Reg, Reg) variable
230 DEF_HELPER_3(glue(packssdw, SUFFIX), void, env, Reg, Reg) variable
240 DEF_HELPER_3(glue(punpcklqdq, SUFFIX), void, env, Reg, Reg) variable
241 DEF_HELPER_3(glue(punpckhqdq, SUFFIX), void, env, Reg, Reg) variable
268 DEF_HELPER_3(glue(phaddw, SUFFIX), void, env, Reg, Reg) variable
269 DEF_HELPER_3(glue(phaddd, SUFFIX), void, env, Reg, Reg) variable
270 DEF_HELPER_3(glue(phaddsw, SUFFIX), void, env, Reg, Reg) variable
271 DEF_HELPER_3(glue(phsubw, SUFFIX), void, env, Reg, Reg) variable
272 DEF_HELPER_3(glue(phsubd, SUFFIX), void, env, Reg, Reg) variable
273 DEF_HELPER_3(glue(phsubsw, SUFFIX), void, env, Reg, Reg) variable
274 DEF_HELPER_3(glue(pabsb, SUFFIX), void, env, Reg, Reg) variable
275 DEF_HELPER_3(glue(pabsw, SUFFIX), void, env, Reg, Reg) variable
276 DEF_HELPER_3(glue(pabsd, SUFFIX), void, env, Reg, Reg) variable
277 DEF_HELPER_3(glue(pmaddubsw, SUFFIX), void, env, Reg, Reg) variable
278 DEF_HELPER_3(glue(pmulhrsw, SUFFIX), void, env, Reg, Reg) variable
279 DEF_HELPER_3(glue(pshufb, SUFFIX), void, env, Reg, Reg) variable
280 DEF_HELPER_3(glue(psignb, SUFFIX), void, env, Reg, Reg) variable
281 DEF_HELPER_3(glue(psignw, SUFFIX), void, env, Reg, Reg) variable
282 DEF_HELPER_3(glue(psignd, SUFFIX), void, env, Reg, Reg) variable
283 DEF_HELPER_4(glue(palignr, SUFFIX), void, env, Reg, Reg, s32) variable
287 DEF_HELPER_3(glue(pblendvb, SUFFIX), void, env, Reg, Reg) variable
288 DEF_HELPER_3(glue(blendvps, SUFFIX), void, env, Reg, Reg) variable
289 DEF_HELPER_3(glue(blendvpd, SUFFIX), void, env, Reg, Reg) variable
290 DEF_HELPER_3(glue(ptest, SUFFIX), void, env, Reg, Reg) variable
291 DEF_HELPER_3(glue(pmovsxbw, SUFFIX), void, env, Reg, Reg) variable
292 DEF_HELPER_3(glue(pmovsxbd, SUFFIX), void, env, Reg, Reg) variable
293 DEF_HELPER_3(glue(pmovsxbq, SUFFIX), void, env, Reg, Reg) variable
294 DEF_HELPER_3(glue(pmovsxwd, SUFFIX), void, env, Reg, Reg) variable
295 DEF_HELPER_3(glue(pmovsxwq, SUFFIX), void, env, Reg, Reg) variable
296 DEF_HELPER_3(glue(pmovsxdq, SUFFIX), void, env, Reg, Reg) variable
297 DEF_HELPER_3(glue(pmovzxbw, SUFFIX), void, env, Reg, Reg) variable
298 DEF_HELPER_3(glue(pmovzxbd, SUFFIX), void, env, Reg, Reg) variable
299 DEF_HELPER_3(glue(pmovzxbq, SUFFIX), void, env, Reg, Reg) variable
300 DEF_HELPER_3(glue(pmovzxwd, SUFFIX), void, env, Reg, Reg) variable
301 DEF_HELPER_3(glue(pmovzxwq, SUFFIX), void, env, Reg, Reg) variable
302 DEF_HELPER_3(glue(pmovzxdq, SUFFIX), void, env, Reg, Reg) variable
303 DEF_HELPER_3(glue(pmuldq, SUFFIX), void, env, Reg, Reg) variable
304 DEF_HELPER_3(glue(pcmpeqq, SUFFIX), void, env, Reg, Reg) variable
305 DEF_HELPER_3(glue(packusdw, SUFFIX), void, env, Reg, Reg) variable
306 DEF_HELPER_3(glue(pminsb, SUFFIX), void, env, Reg, Reg) variable
307 DEF_HELPER_3(glue(pminsd, SUFFIX), void, env, Reg, Reg) variable
308 DEF_HELPER_3(glue(pminuw, SUFFIX), void, env, Reg, Reg) variable
309 DEF_HELPER_3(glue(pminud, SUFFIX), void, env, Reg, Reg) variable
310 DEF_HELPER_3(glue(pmaxsb, SUFFIX), void, env, Reg, Reg) variable
311 DEF_HELPER_3(glue(pmaxsd, SUFFIX), void, env, Reg, Reg) variable
312 DEF_HELPER_3(glue(pmaxuw, SUFFIX), void, env, Reg, Reg) variable
313 DEF_HELPER_3(glue(pmaxud, SUFFIX), void, env, Reg, Reg) variable
314 DEF_HELPER_3(glue(pmulld, SUFFIX), void, env, Reg, Reg) variable
315 DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg) variable
316 DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32) variable
317 DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32) variable
318 DEF_HELPER_4(glue(roundss, SUFFIX), void, env, Reg, Reg, i32) variable
319 DEF_HELPER_4(glue(roundsd, SUFFIX), void, env, Reg, Reg, i32) variable
320 DEF_HELPER_4(glue(blendps, SUFFIX), void, env, Reg, Reg, i32) variable
321 DEF_HELPER_4(glue(blendpd, SUFFIX), void, env, Reg, Reg, i32) variable
322 DEF_HELPER_4(glue(pblendw, SUFFIX), void, env, Reg, Reg, i32) variable
323 DEF_HELPER_4(glue(dpps, SUFFIX), void, env, Reg, Reg, i32) variable
324 DEF_HELPER_4(glue(dppd, SUFFIX), void, env, Reg, Reg, i32) variable
325 DEF_HELPER_4(glue(mpsadbw, SUFFIX), void, env, Reg, Reg, i32) variable
330 DEF_HELPER_3(glue(pcmpgtq, SUFFIX), void, env, Reg, Reg) variable
331 DEF_HELPER_4(glue(pcmpestri, SUFFIX), void, env, Reg, Reg, i32) variable
332 DEF_HELPER_4(glue(pcmpestrm, SUFFIX), void, env, Reg, Reg, i32) variable
333 DEF_HELPER_4(glue(pcmpistri, SUFFIX), void, env, Reg, Reg, i32) variable
334 DEF_HELPER_4(glue(pcmpistrm, SUFFIX), void, env, Reg, Reg, i32) variable
341 DEF_HELPER_3(glue(aesdec, SUFFIX), void, env, Reg, Reg) variable
342 DEF_HELPER_3(glue(aesdeclast, SUFFIX), void, env, Reg, Reg) variable
343 DEF_HELPER_3(glue(aesenc, SUFFIX), void, env, Reg, Reg) variable
344 DEF_HELPER_3(glue(aesenclast, SUFFIX), void, env, Reg, Reg) variable
345 DEF_HELPER_3(glue(aesimc, SUFFIX), void, env, Reg, Reg) variable
346 DEF_HELPER_4(glue(aeskeygenassist, SUFFIX), void, env, Reg, Reg, i32) variable
347 DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32) variable
351 #undef Reg macro
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/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
48 VRegInfo[Reg].first = RC;
52 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
80 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
89 setRegClass(Reg, NewRC);
103 unsigned Reg local
116 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DLivePhysRegs.cpp42 unsigned Reg = O->getReg(); local
43 if (Reg == 0)
45 removeReg(Reg);
54 unsigned Reg = O->getReg(); local
55 if (Reg == 0)
57 addReg(Reg);
70 unsigned Reg = O->getReg(); local
71 if (Reg == 0)
75 Defs.push_back(Reg);
80 removeReg(Reg);
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H A DMachineInstrBundle.cpp133 unsigned Reg = MO.getReg(); local
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg local
187 unsigned Reg = LocalDefs[i]; local
197 unsigned Reg = ExternUses[i]; local
252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DCriticalAntiDepBreaker.cpp67 unsigned Reg = *AI; local
68 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
69 KillIndices[Reg] = BBSize;
70 DefIndices[Reg] = ~0u;
82 unsigned Reg = *AI; local
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
108 for (unsigned Reg = 0; Reg !
180 unsigned Reg = MO.getReg(); local
266 unsigned Reg = MO.getReg(); local
303 unsigned Reg = MO.getReg(); local
624 unsigned Reg = MO.getReg(); local
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H A DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
107 IsLive(unsigned Reg) argument
161 unsigned Reg = *AI; local
174 unsigned Reg = *I; local
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H A DDeadMachineInstructionElim.cpp70 unsigned Reg = MO.getReg(); local
71 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
73 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
131 unsigned Reg = MO.getReg(); local
132 if (!TargetRegisterInfo::isVirtualRegister(Reg))
134 MRI->markUsesInDebugValueAsUndef(Reg);
149 unsigned Reg = MO.getReg(); local
150 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
168 unsigned Reg = MO.getReg(); local
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H A DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument
232 MachineInstr *LastDef = PhysRegDef[Reg];
234 if (!LastDef && !PhysRegUse[Reg]) {
242 // All of the sub-registers must have been defined before the use of Reg!
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg
281 FindLastRefOrPartRef(unsigned Reg) argument
311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument
489 unsigned Reg = Defs.back(); local
651 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
676 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument
689 unsigned Reg = MO.getReg(); local
715 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
733 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
814 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DAllocationOrder.h54 unsigned Reg = Order[Pos++]; local
55 if (!isHint(Reg))
56 return Reg;
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h72 bool isAllocated(unsigned Reg) const {
73 return UsedRegs[Reg/32] & (1 << (Reg&31));
119 unsigned AllocateReg(unsigned Reg) { argument
120 if (isAllocated(Reg)) return 0;
121 MarkAllocated(Reg);
122 return Reg;
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
127 if (isAllocated(Reg)) return 0;
128 MarkAllocated(Reg);
142 unsigned Reg = Regs[FirstUnalloc]; local
155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h54 unsigned getFirstReg(unsigned Reg);
57 inline unsigned getRegAsGR64(unsigned Reg) { argument
58 return GR64Regs[getFirstReg(Reg)];
62 inline unsigned getRegAsGR32(unsigned Reg) { argument
63 return GR32Regs[getFirstReg(Reg)];
67 inline unsigned getRegAsGRH32(unsigned Reg) { argument
68 return GRH32Regs[getFirstReg(Reg)];
/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
281 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
299 isPHIJoin(unsigned Reg) argument
302 setPHIJoin(unsigned Reg) argument
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H A DMachineRegisterInfo.h36 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
91 return MO->Contents.Reg.Next;
195 /// Verify the sanity of the use list for Reg.
196 void verifyUseList(unsigned Reg) const;
228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
244 reg_instructions(unsigned Reg) const {
245 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
261 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
599 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument
652 setPhysRegUsed(unsigned Reg) argument
666 setPhysRegUnused(unsigned Reg) argument
739 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
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H A DRegisterScavenging.h45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
52 unsigned Reg; member in struct:llvm::RegScavenger::ScavengedInfo
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const { argument
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) cons
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H A DLiveIntervalAnalysis.h108 LiveInterval &getInterval(unsigned Reg) { argument
109 if (hasInterval(Reg))
110 return *VirtRegIntervals[Reg];
112 return createAndComputeVirtRegInterval(Reg);
115 const LiveInterval &getInterval(unsigned Reg) const {
116 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
119 bool hasInterval(unsigned Reg) const {
120 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
124 LiveInterval &createEmptyInterval(unsigned Reg) { argument
131 createAndComputeVirtRegInterval(unsigned Reg) argument
138 removeInterval(unsigned Reg) argument
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H A DStackMaps.h91 unsigned Reg; member in struct:llvm::StackMaps::Location
93 Location() : LocType(Unprocessed), Size(0), Reg(0), Offset(0) {}
94 Location(LocationType LocType, unsigned Size, unsigned Reg, int64_t Offset) argument
95 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {}
99 unsigned short Reg; member in struct:llvm::StackMaps::LiveOutReg
103 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
104 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size) argument
105 : Reg(Reg), RegN
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H A DLivePhysRegs.h74 void addReg(unsigned Reg) { argument
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
84 void removeReg(unsigned Reg) { argument
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
90 for (MCSuperRegIterator SuperRegs(Reg, TRI, /*IncludeSelf=*/false);
98 /// \brief Returns true if register @p Reg is contained in the set. This also
99 /// works if only the super register of @p Reg has been defined, because we
101 bool contains(unsigned Reg) cons
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/external/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; } argument
40 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; } argument
H A DSystemZShortenInst.cpp78 unsigned Reg = MI.getOperand(0).getReg(); local
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
110 unsigned Reg = *LI;
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112 LiveLow |= LowGPRs[Reg];
113 LiveHigh |= HighGPRs[Reg];
133 if (unsigned Reg
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/external/llvm/lib/Target/R600/
H A DR600RegisterInfo.h34 unsigned getHWRegIndex(unsigned Reg) const override;
43 // \returns true if \p Reg can be defined in one ALU caluse and used in another.
44 bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
H A DSIFixSGPRCopies.cpp89 unsigned Reg,
93 unsigned Reg,
130 /// This functions walks the use list of Reg until it finds an Instruction
136 unsigned Reg,
138 // The Reg parameter to the function must always be defined by either a PHI
140 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
141 "Reg cannot be a physical register");
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
162 unsigned Reg,
133 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
159 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
223 unsigned Reg = MI.getOperand(i).getReg(); local
228 unsigned Reg = MI.getOperand(0).getReg(); local
241 unsigned Reg = MI.getOperand(i).getReg(); local
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/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp59 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) { argument
191 assert(Reg >= 0);
192 if (Reg < 32) {
193 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
194 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
197 Streamer.EmitULEB128(Reg, Twine(Reg));
202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset, argument
204 assert(Reg >
253 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); local
335 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); local
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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
100 Reg = DefMI->getOperand(1).getReg();
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
102 DefMI = MRI->getVRegDef(Reg);
106 Reg = DefMI->getOperand(2).getReg();
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
108 DefMI = MRI->getVRegDef(Reg);
118 unsigned Reg = MI->getOperand(0).getReg(); local
144 unsigned Reg = MI->getOperand(1).getReg(); local
185 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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