| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 3050 EVT ResVT = N->getValueType(0); local
3053 assert(ResVT.isVector() && "Vector load must have vector type");
3058 assert(ResVT.isSimple() && "Can only handle simple types");
3059 switch (ResVT.getSimpleVT().SimpleTy) {
3076 EVT EltVT = ResVT.getVectorElementType();
3077 unsigned NumElts = ResVT.getVectorNumElements();
3127 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
3133 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
3156 EVT ResVT = N->getValueType(0); local
3158 if (ResVT
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1279 EVT ResVT = N->getValueType(0); local
1285 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1291 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1510 EVT ResVT = N->getValueType(0); local
1516 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1522 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2616 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), local
2620 ResVT, WideSETCC, DAG.getConstant(0,
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| H A D | LegalizeIntegerTypes.cpp | 172 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); local
174 N->getMemoryVT(), ResVT,
|
| H A D | DAGCombiner.cpp | 8336 EVT ResVT = Use->getValueType(0); local
8337 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
8340 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8354 ResVT.getTypeForEVT(*DAG->getContext()));
8360 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 7187 EVT ResVT = N->getValueType(0); local
7188 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7193 if (!ResVT.isSimple())
7213 unsigned NumElements = ResVT.getVectorNumElements();
7216 ResVT.getVectorElementType(), NumElements / 2);
7229 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7649 EVT ResVT = N->getValueType(0);
7653 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7662 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetC
7672 EVT ResVT = N->getValueType(0); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3088 EVT ResVT = RVLocs[i].getValVT(); local
3089 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
3090 unsigned MemSize = ResVT.getSizeInBits()/8;
3095 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
|
| H A D | X86ISelLowering.cpp | 6850 MVT ResVT = Op.getSimpleValueType(); local
6852 assert((ResVT.is256BitVector() ||
6853 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6857 unsigned NumElems = ResVT.getVectorNumElements();
6858 if(ResVT.is256BitVector())
6859 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6862 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6863 ResVT.getVectorNumElements()/2);
6867 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6869 return Concat256BitVectors(V1, V2, ResVT, NumElem
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4993 EVT ResVT = Op.getValueType(); local
5010 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5013 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5022 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5030 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5043 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5046 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5053 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5059 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5065 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cm
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1916 EVT ResVT = Op.getValueType(); local
1918 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1934 if (InVT == MVT::f32 && ResVT == MVT::i32) {
|