| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, local
394 if (ResultReg == 0) return false;
397 UpdateValueMap(I, ResultReg);
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local
429 if (ResultReg == 0) return false;
432 UpdateValueMap(I, ResultReg);
438 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), local
440 if (ResultReg != 0) {
442 UpdateValueMap(I, ResultReg);
455 unsigned ResultReg local
807 unsigned ResultReg = getRegForValue(ResCI); local
814 unsigned ResultReg = getRegForValue(Call->getArgOperand(0)); local
862 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), local
901 unsigned ResultReg = 0; local
1016 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), local
1070 unsigned ResultReg; local
1304 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); local
1345 unsigned ResultReg = createResultReg(RC); local
1357 unsigned ResultReg = createResultReg(RC); local
1379 unsigned ResultReg = createResultReg(RC); local
1404 unsigned ResultReg = createResultReg(RC); local
1431 unsigned ResultReg = createResultReg(RC); local
1455 unsigned ResultReg = createResultReg(RC); local
1480 unsigned ResultReg = createResultReg(RC); local
1504 unsigned ResultReg = createResultReg(RC); local
1531 unsigned ResultReg = createResultReg(RC); local
1554 unsigned ResultReg = createResultReg(RC); local
1570 unsigned ResultReg = createResultReg(RC); local
1587 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 72 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
155 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, argument
163 ResultReg = createResultReg(&Mips::GPR32RegClass);
168 ResultReg = createResultReg(&Mips::GPR32RegClass);
173 ResultReg = createResultReg(&Mips::GPR32RegClass);
178 ResultReg = createResultReg(&Mips::FGR32RegClass);
183 ResultReg = createResultReg(&Mips::AFGR64RegClass);
190 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
258 unsigned ResultReg; local
259 if (!EmitLoad(VT, ResultReg, Add
372 unsigned ResultReg = createResultReg(RC); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
186 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); local
188 ResultReg)
192 return ResultReg;
217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
220 return ResultReg;
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
239 return ResultReg;
259 unsigned ResultReg; local
470 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); local
484 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false, local
515 EmitLoad(MVT VT, unsigned &ResultReg, Address Addr, bool UseUnscaled) argument
609 unsigned ResultReg; local
1009 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass); local
1074 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); local
1094 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); local
1110 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); local
1143 unsigned ResultReg = createResultReg( local
1188 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); local
1295 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local
1468 unsigned ResultReg; local
1717 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass); local
1740 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass); local
1806 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); local
1837 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local
1880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); local
1927 unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT)); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 84 unsigned &ResultReg);
93 unsigned &ResultReg);
365 MachineMemOperand *MMO, unsigned &ResultReg) {
412 ResultReg = createResultReg(RC);
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
534 unsigned &ResultReg) {
540 ResultReg = RR;
1106 unsigned ResultReg = 0; local
1107 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg))
1110 UpdateValueMap(I, ResultReg);
364 X86FastEmitLoad(EVT VT, const X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg) argument
532 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
1193 unsigned ResultReg = 0; local
1283 unsigned ResultReg = getRegForValue(I->getOperand(0)); local
1561 unsigned ResultReg = createResultReg(RC); local
1704 unsigned ResultReg = 0; local
1843 unsigned ResultReg = FastEmitInst_rr(Opc, RC, RHSReg, RHSIsKill, local
1929 unsigned ResultReg = FastEmitInst_rr(Opc[3], RC, AndNReg, /*IsKill=*/true, local
1993 unsigned ResultReg = local
2020 unsigned ResultReg = createResultReg(RC); local
2053 unsigned ResultReg = createResultReg(&X86::FR64RegClass); local
2072 unsigned ResultReg = createResultReg(&X86::FR32RegClass); local
2119 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, local
2352 unsigned ResultReg = createResultReg(RC); local
2415 unsigned ResultReg = 0; local
2533 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
2629 unsigned ResultReg = createResultReg(RC); local
3060 unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); local
3229 unsigned ResultReg = createResultReg(RC); local
3270 unsigned ResultReg = createResultReg(RC); local
3295 unsigned ResultReg = createResultReg(RC); local
3334 unsigned ResultReg = createResultReg(RC); local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
407 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
409 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
410 Addr.Base.Reg = ResultReg;
427 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, argument
433 // If ResultReg is given, it determines the register class of the load.
441 (ResultReg ? MRI.getRegClass(ResultReg) :
486 if (ResultReg == 0)
487 ResultReg
560 unsigned ResultReg = 0; local
909 unsigned ResultReg = 0; local
1016 unsigned ResultReg = 0; local
1120 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); local
1336 unsigned ResultReg = 0; local
1710 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); local
1751 unsigned ResultReg = createResultReg(RC); local
1926 unsigned ResultReg = createResultReg(RC); local
1998 unsigned ResultReg = createResultReg(RC); local
2081 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
2159 unsigned ResultReg = MI->getOperand(0).getReg(); local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
289 unsigned ResultReg = createResultReg(RC); local
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
302 TII.get(TargetOpcode::COPY), ResultReg)
305 return ResultReg;
312 unsigned ResultReg = createResultReg(RC); local
322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
330 TII.get(TargetOpcode::COPY), ResultReg)
333 return ResultReg;
341 unsigned ResultReg local
372 unsigned ResultReg = createResultReg(RC); local
399 unsigned ResultReg = createResultReg(RC); local
427 unsigned ResultReg = createResultReg(RC); local
716 unsigned ResultReg = createResultReg(RC); local
891 unsigned ResultReg = createResultReg(RC); local
958 ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument
1074 unsigned ResultReg; local
1585 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local
1611 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local
1677 unsigned ResultReg = createResultReg(RC); local
1780 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
1824 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local
2038 unsigned ResultReg = createResultReg(DstRC); local
2059 unsigned ResultReg = createResultReg(DstRC); local
2455 unsigned ResultReg; local
2690 unsigned ResultReg; local
2746 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local
2788 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
2933 unsigned ResultReg = MI->getOperand(0).getReg(); local
3049 unsigned ResultReg = createResultReg(RC); local
[all...] |
| /external/llvm/lib/Target/R600/ |
| H A D | SIInstrInfo.cpp | 1499 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
1512 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1516 MRI.replaceRegWith(Dest.getReg(), ResultReg);
|