Searched refs:SLL (Results 1 - 25 of 33) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp45 AddInstr(SeqLs, Inst(SLL, Shamt));
79 // Replace a ADDiu & SLL pair with a LUi.
82 // SLL 18
86 // Check if the first two instructions are ADDiu and SLL and the shift amount
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
132 SLL = Mips::SLL;
137 SLL = Mips::DSLL;
H A DMipsAnalyzeImmediate.h43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
H A DMipsCodeEmitter.cpp380 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
H A DMipsISelLowering.cpp1066 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1144 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1149 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1384 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1389 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
2082 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); local
2083 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
/external/openssl/crypto/bn/asm/
H A Dmips.pl63 $SLL="dsll";
78 $SLL="sll";
890 $SLL $a2,1
897 $SLL $t2,$t1
905 $SLL $a0,$t9
906 $SLL $a1,$t9
930 $SLL $t3,$a0,4*$BNSZ # bits
951 $SLL $a1,4*$BNSZ # bits
953 $SLL $v0,$QT,4*$BNSZ # bits
963 $SLL
[all...]
/external/openssl/crypto/sha/asm/
H A Dsha512-mips.pl83 $SLL="dsll"; # shift left logical
97 $SLL="sll"; # shift left logical
161 $SLL $tmp1,$e,`$SZ*8-@Sigma1[2]`
165 $SLL $tmp1,$e,`$SZ*8-@Sigma1[1]`
169 $SLL $tmp1,$e,`$SZ*8-@Sigma1[0]`
177 $SLL $tmp1,$a,`$SZ*8-@Sigma0[2]`
181 $SLL $tmp1,$a,`$SZ*8-@Sigma0[1]`
185 $SLL $tmp1,$a,`$SZ*8-@Sigma0[0]`
212 $SLL $tmp1,@X[1],`$SZ*8-@sigma0[2]`
215 $SLL
[all...]
H A Dsha512-sparcv9.pl58 $SLL="sllx"; # shift left logical
84 $SLL="sll"; # shift left logical
224 $SLL $e,`$SZ*8-@Sigma1[2]`,$tmp1
228 $SLL $e,`$SZ*8-@Sigma1[1]`,$tmp1
232 $SLL $e,`$SZ*8-@Sigma1[0]`,$tmp1
240 $SLL $a,`$SZ*8-@Sigma0[2]`,$tmp1
244 $SLL $a,`$SZ*8-@Sigma0[1]`,$tmp1
248 $SLL $a,`$SZ*8-@Sigma0[0]`,$tmp1
/external/pcre/dist/sljit/
H A DsljitNativeSPARC_32.c59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst)));
70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst)));
92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1)));
126 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
H A DsljitNativeMIPS_32.c90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst)));
108 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(16), DR(dst)));
147 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS));
192 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
195 return push_inst(compiler, SLL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
268 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
328 EMIT_SHIFT(SLL, SLLV);
H A DsljitNativeMIPS_64.c208 return push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(0), DR(dst));
239 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL, SLL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS));
284 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
287 return push_inst(compiler, SELECT_OP(DSRL32, SLL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
360 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV);
H A DsljitNativeSPARC_common.c150 #define SLL (OPC1(0x2) | OPC3(0x25)) macro
170 #define SLL_W SLL
/external/clang/test/CodeGen/
H A Dxcore-stringtype.c25 long long LL, unsigned long long ULL, signed long long SLL,
22 builtinType(_Bool B, char C, unsigned char UC, signed char SC, short S, unsigned short US, signed short SS, int I, unsigned int UI, signed int SI, long L, unsigned long UL, signed long SL, long long LL, unsigned long long ULL, signed long long SLL, float F, double D, long double LD) argument
/external/chromium_org/v8/src/mips/
H A Dconstants-mips.cc224 case SLL:
H A Dconstants-mips.h372 SLL = ((0 << 3) + 0),
H A Dmacro-assembler-mips.h472 bool sllzz = (opcode == SLL &&
H A Dassembler-mips.cc601 bool ret = (opcode == SPECIAL && function == SLL &&
1606 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
/external/chromium_org/v8/src/mips64/
H A Dconstants-mips64.cc224 case SLL:
H A Dconstants-mips64.h349 SLL = ((0 << 3) + 0),
H A Dmacro-assembler-mips64.h493 bool sllzz = (opcode == SLL &&
H A Dassembler-mips64.cc573 bool ret = (opcode == SPECIAL && function == SLL &&
1670 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/
H A Dmemcpy.S113 #define SLL dsll define
148 #define SLL sll define
328 SLL rem, len, 3 # rem = number of bits to keep
/external/valgrind/main/none/tests/mips64/
H A Dshift_instructions.c9 ROTR, ROTRV, SLL, SLLV, enumerator in enum:__anon33136
159 case SLL:
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
/external/clang/lib/Sema/
H A DSemaOverload.cpp6954 // (we could precompute SLL x UI for all known platforms, but it's
6959 Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128
6966 /* SI*/ { Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128 },
6967 /* SL*/ { Flt, Dbl, LDbl, SL, SL, SLL, S128, Dep, UL, ULL, U128 },
6968 /* SLL*/ { Flt, Dbl, LDbl, SLL, SLL, SLL, S128, Dep, Dep, ULL, U128 },
6996 assert(L == SLL || R == SLL);
[all...]
/external/oprofile/events/mips/74K/
H A Devents60 event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB

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