Searched refs:SRA (Results 1 - 25 of 55) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr;
/external/pcre/dist/sljit/
H A DsljitNativeSPARC_32.c60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst));
71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1)));
134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
H A DsljitNativeMIPS_32.c91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst));
109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst));
312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
336 EMIT_SHIFT(SRA, SRAV);
H A DsljitNativeMIPS_64.c407 FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
431 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV);
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp210 { ISD::SRA, MVT::v4i32, 1 },
213 { ISD::SRA, MVT::v8i32, 1 },
225 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
227 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
269 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
270 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
271 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
325 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
326 { ISD::SRA, MV
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/external/chromium_org/v8/src/mips/
H A Dconstants-mips.cc226 case SRA:
H A Dconstants-mips.h375 SRA = ((0 << 3) + 3),
/external/chromium_org/v8/src/mips64/
H A Dconstants-mips64.cc230 case SRA:
H A Dconstants-mips64.h352 SRA = ((0 << 3) + 3),
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h311 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
375 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon26033
H A DMSP430ISelLowering.cpp92 setOperationAction(ISD::SRA, MVT::i8, Custom);
95 setOperationAction(ISD::SRA, MVT::i16, Custom);
189 case ISD::SRA: return LowerShifts(Op, DAG);
752 case ISD::SRA:
753 return DAG.getNode(MSP430ISD::SRA, dl,
972 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1159 case MSP430ISD::SRA: return "MSP430ISD::SRA";
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
600 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
835 case ISD::SRA:
1207 case ISD::SRA:
1384 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1386 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1389 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1391 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1395 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1403 Hi = DAG.getNode(ISD::SRA, D
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H A DLegalizeVectorOps.cpp18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
254 case ISD::SRA:
550 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
723 // Make sure that the SRA and SHL instructions are available.
724 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
737 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
781 return DAG.getNode(ISD::SRA, DL, VT,
H A DDAGCombiner.cpp980 if (Opc == ISD::SRA)
1221 case ISD::SRA: return visitSRA(N);
1307 case ISD::SRA:
2026 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2039 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, local
2045 return SRA;
2047 AddToWorkList(SRA.getNode());
2048 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2227 return DAG.getNode(ISD::SRA, SDLo
4234 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT, local
[all...]
H A DFastISel.cpp417 ISDOpcode = ISD::SRA;
1127 return SelectBinaryOp(I, ISD::SRA);
1299 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DSelectionDAGBuilder.h714 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
H A DSelectionDAGDumper.cpp178 case ISD::SRA: return "sra";
/external/valgrind/main/none/tests/mips64/
H A Dshift_instructions.c10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon33136
177 case SRA:
/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/
H A Dmemcpy.S112 #define SRA dsra define
149 #define SRA sra define
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp1089 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; local
1104 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1108 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1109 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1590 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h95 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp818 case ISD::SRA: {
828 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {

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