/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
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/external/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical 98 $SRL="srl"; # shift right logical 159 $SRL $h,$e,@Sigma1[0] 163 $SRL $tmp0,$e,@Sigma1[1] 167 $SRL $tmp0,$e,@Sigma1[2] 174 $SRL $h,$a,@Sigma0[0] 179 $SRL $tmp0,$a,@Sigma0[1] 183 $SRL $tmp0,$a,@Sigma0[2] 210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i) 213 $SRL [all...] |
H A D | sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical 85 $SRL="srl"; # shift right logical 222 $SRL $e,@Sigma1[0],$h !! $i 226 $SRL $e,@Sigma1[1],$tmp0 230 $SRL $e,@Sigma1[2],$tmp0 237 $SRL $a,@Sigma0[0],$h 242 $SRL $a,@Sigma0[1],$tmp0 246 $SRL $a,@Sigma0[2],$tmp0
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 209 { ISD::SRL, MVT::v4i32, 1 }, 212 { ISD::SRL, MVT::v8i32, 1 }, 215 { ISD::SRL, MVT::v2i64, 1 }, 217 { ISD::SRL, MVT::v4i64, 1 }, 222 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. 223 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. 264 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 265 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 266 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 267 { ISD::SRL, MV [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, local 186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
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H A D | SystemZInstrInfo.cpp | 454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); 455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC)) 458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); 476 eraseIfDead(SRL, MRI);
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/external/chromium_org/v8/src/mips/ |
H A D | constants-mips.cc | 225 case SRL:
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/external/chromium_org/v8/src/mips64/ |
H A D | constants-mips64.cc | 227 case SRL:
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/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
H A D | memcpy.S | 111 #define SRL dsrl define 147 #define SRL srl define 238 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter 360 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 614 if (InOp.getOpcode() == ISD::SRL && 622 Opc = ISD::SRL; 662 InnerOp.getOpcode() == ISD::SRL && 689 case ISD::SRL: 707 unsigned Opc = ISD::SRL; 740 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 772 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 972 case ISD::SRL: 973 // Shrink SRL b [all...] |
H A D | LegalizeIntegerTypes.cpp | 77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 299 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 608 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt); 707 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 836 case ISD::SRL: 1208 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1356 DAG.getNode(ISD::SRL, DL, NVT, InL, 1362 if (N->getOpcode() == ISD::SRL) { 1367 Lo = DAG.getNode(ISD::SRL, DL, 1375 DAG.getNode(ISD::SRL, D [all...] |
H A D | DAGCombiner.cpp | 982 else if (Opc == ISD::SRL) 1222 case ISD::SRL: return visitSRL(N); 1308 case ISD::SRL: 2032 SDValue SRL = local 2033 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, 2036 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); 2037 AddToWorkList(SRL.getNode()); 2086 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 2100 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); 2244 N1 = DAG.getNode(ISD::SRL, D [all...] |
H A D | LegalizeDAG.cpp | 406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 1302 case ISD::SRL: 2477 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2498 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2532 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2688 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2693 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2694 Tmp1 = DAG.getNode(ISD::SRL, d [all...] |
H A D | LegalizeVectorOps.cpp | 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 255 case ISD::SRL: 519 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); 893 // Make sure that the SINT_TO_FP and SRL instructions are available. 895 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 915 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon26033
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H A D | MSP430ISelLowering.cpp | 94 setOperationAction(ISD::SRL, MVT::i8, Custom); 97 setOperationAction(ISD::SRL, MVT::i16, Custom); 188 case ISD::SRL: 755 case ISD::SRL: 756 return DAG.getNode(MSP430ISD::SRL, dl, 767 if (Opc == ISD::SRL && ShiftAmount) { 971 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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/external/pcre/dist/sljit/ |
H A D | sljitNativeSPARC_32.c | 71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); 130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
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H A D | sljitNativeMIPS_32.c | 135 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); 271 return push_inst(compiler, SRL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 332 EMIT_SHIFT(SRL, SRLV);
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H A D | sljitNativeMIPS_64.c | 227 FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); 363 return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV);
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/external/valgrind/main/none/tests/mips64/ |
H A D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon33136 189 case SRL:
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 390 } else if (Opcode == ISD::SRL) { 437 Op0.getOperand(0).getOpcode() == ISD::SRL) { 439 Op1.getOperand(0).getOpcode() != ISD::SRL) { 445 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 447 Op1.getOperand(0).getOpcode() != ISD::SRL) { 458 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 472 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask && 1179 if (Val.getOpcode() == ISD::SRL && 1231 case ISD::SRL: {
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/external/openssl/crypto/bn/asm/ |
H A D | mips.pl | 62 $SRL="dsrl"; 77 $SRL="srl"; 899 $SRL $at,$a1,$t1 914 $SRL $DH,$a2,4*$BNSZ # bits 923 $SRL $HH,$a0,4*$BNSZ # bits 924 $SRL $QT,4*$BNSZ # q=0xffffffff 931 $SRL $at,$a1,4*$BNSZ # bits 956 $SRL $HH,$a0,4*$BNSZ # bits 957 $SRL $QT,4*$BNSZ # q=0xffffffff 964 $SRL [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 924 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); 928 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo, 1063 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); 1064 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); 1104 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); 1105 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); 1108 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); 1310 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr, 1367 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, 1393 DAG.getNode(ISD::SRL, D [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 1789 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1790 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1837 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1838 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1948 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1950 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1989 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1991 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2083 SDValue SRL local [all...] |