Searched refs:TCG_AREG0 (Results 1 - 5 of 5) sorted by relevance
/external/qemu/tcg/i386/ |
H A D | tcg-target.h | 141 # define TCG_AREG0 TCG_REG_R14 macro 143 # define TCG_AREG0 TCG_REG_EBP macro
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H A D | tcg-target.c | 1111 tcg_out_modrm_sib_offset(s, OPC_LEA + hrexw, r0, TCG_AREG0, r0, 0, 1192 tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); 1208 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1276 tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); 1302 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 2132 tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, 2140 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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/external/qemu/target-mips/ |
H A D | translate.c | 8546 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 8549 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, 8552 cpu_PC = tcg_global_mem_new(TCG_AREG0, 8555 cpu_HI[i] = tcg_global_mem_new(TCG_AREG0, 8558 cpu_LO[i] = tcg_global_mem_new(TCG_AREG0, 8561 cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0, 8565 cpu_dspctrl = tcg_global_mem_new(TCG_AREG0, 8568 bcond = tcg_global_mem_new(TCG_AREG0, 8570 btarget = tcg_global_mem_new(TCG_AREG0, 8572 hflags = tcg_global_mem_new_i32(TCG_AREG0, [all...] |
/external/qemu/target-arm/ |
H A D | translate.c | 112 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 115 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, 119 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0, 121 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0, 123 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0, 126 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0, 128 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
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/external/qemu/target-i386/ |
H A D | translate.c | 7755 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 7756 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, 7758 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), 7760 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
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