Searched refs:TRC (Results 1 - 8 of 8) sorted by relevance
/external/chromium_org/third_party/qcms/src/ |
H A D | transform_util.h | 50 float *build_input_gamma_table(struct curveType *TRC);
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H A D | transform_util.c | 253 float *build_input_gamma_table(struct curveType *TRC) argument 257 if (!TRC) return NULL; 260 if (TRC->type == PARAMETRIC_CURVE_TYPE) { 261 compute_curve_gamma_table_type_parametric(gamma_table, TRC->parameter, TRC->count); 263 if (TRC->count == 0) { 265 } else if (TRC->count == 1) { 266 compute_curve_gamma_table_type1(gamma_table, u8Fixed8Number_to_float(TRC->data[0])); 268 compute_curve_gamma_table_type2(gamma_table, TRC->data, TRC [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 74 const TargetRegisterClass *TRC); 98 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 134 const TargetRegisterClass *TRC) { 140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 142 return TRC->contains(Reg); 276 const TargetRegisterClass *TRC = local 278 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 448 const TargetRegisterClass *TRC) { 449 unsigned Out = MRI->createVirtualRegister(TRC); 133 usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC) argument 444 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
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H A D | ARMISelLowering.cpp | 6314 const TargetRegisterClass *TRC = isThumb ? local 6334 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6339 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 6344 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6361 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6365 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 6370 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6374 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 6379 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 6393 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6420 const TargetRegisterClass *TRC = Subtarget->isThumb() ? local 6943 const TargetRegisterClass *TRC = nullptr; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 2050 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); local 2051 MRI->constrainRegClass(EvenReg, TRC); 2052 MRI->constrainRegClass(OddReg, TRC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 486 const TargetRegisterClass *TRC = 495 TRC == MRI->getRegClass(SrcReg)) { 501 VRBase = MRI->createVirtualRegister(TRC); 515 VRBase = MRI->createVirtualRegister(TRC); 620 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 622 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 569 const TargetRegisterClass *TRC; local 571 TRC = &Hexagon::PredRegsRegClass; 573 TRC = &Hexagon::IntRegsRegClass; 575 TRC = &Hexagon::DoubleRegsRegClass; 580 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2589 const TargetRegisterClass *TRC; local 2591 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2592 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2595 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2624 const TargetRegisterClass *TRC; local 2626 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2627 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2628 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2631 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
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