Searched refs:TRI (Results 1 - 25 of 233) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h44 const TargetRegisterInfo *TRI; member in class:llvm::LivePhysRegs
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {}
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { argument
55 assert(TRI && "Invalid TargetRegisterInfo pointer.");
56 LiveRegs.setUniverse(TRI->getNumRegs());
62 TRI = _TRI;
64 LiveRegs.setUniverse(TRI->getNumRegs());
75 assert(TRI
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H A DStackMapLivenessAnalysis.h35 const TargetRegisterInfo *TRI; member in class:llvm::StackMapLiveness
/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp87 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
91 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
95 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
117 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { argument
124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
134 const SIRegisterInfo *TRI,
144 RC = TRI->getSubRegClass(RC, SubReg);
149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
160 const SIRegisterInfo *TRI,
133 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
159 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
177 isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI) const argument
198 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( local
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H A DR600ExpandSpecialInstrs.cpp70 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
178 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
186 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
199 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
202 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
205 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
229 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
230 (TRI.getEncodingValue(Src1) & 0xff) < 127)
231 assert(TRI
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/external/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp34 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
41 if (MF->getTarget().getRegisterInfo() != TRI) {
42 TRI = MF->getTarget().getRegisterInfo();
43 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
44 unsigned NumPSets = TRI->getNumRegPressureSets();
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
56 CSRNum.resize(TRI->getNumRegs(), 0);
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
102 unsigned Cost = TRI->getCostPerUse(PhysReg);
121 unsigned Cost = TRI
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H A DLiveRegMatrix.cpp51 TRI = MF.getTarget().getRegisterInfo();
56 unsigned NumRegUnits = TRI->getNumRegUnits();
76 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
77 << " to " << PrintReg(PhysReg, TRI) << ':');
81 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
82 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
91 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
92 << " from " << PrintReg(PhysReg, TRI) << ':');
94 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
95 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
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H A DAllocationOrder.cpp35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
44 dbgs() << ' ' << PrintReg(Hints[I], TRI);
H A DTargetRegisterInfo.cpp43 else if (TRI && Reg < TRI->getNumRegs())
44 OS << '%' << TRI->getName(Reg);
48 if (TRI)
49 OS << ':' << TRI->getSubRegIndexName(SubIdx);
56 // Generic printout when TRI is missing.
57 if (!TRI) {
63 if (Unit >= TRI->getNumRegUnits()) {
69 MCRegUnitRootIterator Roots(Unit, TRI);
71 OS << TRI
161 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument
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H A DRegAllocBase.h61 const TargetRegisterInfo *TRI; member in class:llvm::RegAllocBase
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
H A DRegisterCoalescer.h29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
H A DMachineCopyPropagation.cpp36 const TargetRegisterInfo *TRI; member in class:__anon25763::MachineCopyPropagation
69 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
78 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR)
115 const TargetRegisterInfo *TRI) {
119 if (TRI->isSubRegister(SrcSrc, Def)) {
121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
124 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
164 isNopCopy(CopyMI, Def, Src, TRI)) {
184 I->clearRegisterKills(Def, TRI);
194 for (MCRegAliasIterator AI(Src, TRI, tru
114 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument
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H A DRegisterScavenging.cpp35 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
75 TRI = TM.getRegisterInfo();
78 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
88 NumPhysRegs = TRI->getNumRegs();
95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
108 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
221 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
238 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
263 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp53 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
120 DstReg = TRI
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/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp53 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
120 DstReg = TRI
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/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h94 const TargetRegisterInfo *TRI) const override {
95 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
102 const TargetRegisterInfo *TRI) const override {
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
110 const TargetRegisterInfo *TRI,
117 const TargetRegisterInfo *TRI,
H A DMips16FrameLowering.h36 const TargetRegisterInfo *TRI) const override;
41 const TargetRegisterInfo *TRI) const override;
H A DMipsFrameLowering.cpp104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); local
113 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.h36 const TargetRegisterInfo *TRI) const override;
40 const TargetRegisterInfo *TRI) const override;
H A DThumb1InstrInfo.h49 const TargetRegisterInfo *TRI) const override;
55 const TargetRegisterInfo *TRI) const override;
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h32 const TargetRegisterInfo *TRI) const override;
43 const TargetRegisterInfo *TRI) const override;
H A DHexagonFrameLowering.cpp212 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument
213 MCSuperRegIterator SRI(Reg, TRI);
226 const TargetRegisterInfo *TRI) const {
247 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
252 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
260 CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
268 TRI);
280 const TargetRegisterInfo *TRI) cons
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.h40 const TargetRegisterInfo *TRI) const override;
44 const TargetRegisterInfo *TRI) const override;
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.h37 const TargetRegisterInfo *TRI) const override;
41 const TargetRegisterInfo *TRI) const override;
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.h47 const TargetRegisterInfo *TRI,
53 const TargetRegisterInfo *TRI) const override;
58 const TargetRegisterInfo *TRI) const override;
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp252 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
253 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
264 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
265 Reg = TRI->getDwarfRegNum(*SR, false);
267 unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
268 unsigned Size = TRI->getSubRegIdxSize(Idx);
269 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
298 for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
299 unsigned Idx = TRI
334 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
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