| /external/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 186 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), local
192 Tmp3 = Builder.CreateAnd(Tmp3,
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1");
214 Value* Tmp3 = Builder.CreateLShr(V, local
239 Tmp3 = Builder.CreateAnd(Tmp3,
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3");
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 584 SDValue Tmp3 = Idx; local
594 EVT IdxVT = Tmp3.getValueType();
607 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
610 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
611 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
1614 SDValue Tmp3 = Node->getOperand(2);
1625 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
2683 SDValue Tmp1, Tmp2, Tmp3, Tmp
[all...] |
| H A D | LegalizeFloatTypes.cpp | 1323 SDValue Tmp1, Tmp2, Tmp3; local
1328 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1334 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
|
| /external/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 135 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); local
136 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1);
283 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); local
351 R_1->addIncoming(Tmp3, Preheader);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1576 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
1577 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1581 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1777 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
1778 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1850 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1853 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
2295 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2296 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2299 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp
2436 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2444 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; local
[all...] |
| H A D | X86ISelLowering.cpp | 10635 SDValue Tmp2, Tmp3;
10638 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10641 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10654 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10655 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13134 SDValue Tmp3 = Node->getOperand(2);
13145 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
|
| /external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/main/source/ |
| H A D | structs.h | 252 double Tmp3[MAXFFTSIZE]; member in struct:__anon15778
|
| H A D | fft.c | 343 Sin = (REAL *) fftstate->Tmp3;
|
| /external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
| H A D | structs.h | 253 double Tmp3[MAXFFTSIZE]; member in struct:__anon33453
|
| H A D | fft.c | 338 if (fftstate->Tmp0 == NULL || fftstate->Tmp1 == NULL || fftstate->Tmp2 == NULL || fftstate->Tmp3 == NULL
347 Sin = (REAL *) fftstate->Tmp3;
|
| /external/clang/lib/CodeGen/ |
| H A D | CGExprComplex.cpp | 586 llvm::Value *Tmp3 = Builder.CreateFAdd(Tmp1, Tmp2); // ac+bd local
596 DSTr = Builder.CreateFDiv(Tmp3, Tmp6);
602 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd local
613 DSTr = Builder.CreateUDiv(Tmp3, Tmp6);
616 DSTr = Builder.CreateSDiv(Tmp3, Tmp6);
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1562 SDValue Tmp3 = ST->getValue(); local
1563 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
1567 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1568 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 5355 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); local
5356 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5384 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); local
5385 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5412 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); local
5413 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3761 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); local
3769 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4056 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); local
4063 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
|