Searched refs:VIXL_ASSERT (Results 1 - 24 of 24) sorted by relevance

/external/vixl/src/a64/
H A Dmacro-assembler-a64.h344 VIXL_ASSERT(allow_macro_instructions_);
345 VIXL_ASSERT(!rd.IsZero());
349 VIXL_ASSERT(allow_macro_instructions_);
350 VIXL_ASSERT(!rd.IsZero());
351 VIXL_ASSERT(!rn.IsZero());
355 VIXL_ASSERT(allow_macro_instructions_);
356 VIXL_ASSERT(!rd.IsZero());
357 VIXL_ASSERT(!rn.IsZero());
358 VIXL_ASSERT(!rm.IsZero());
382 VIXL_ASSERT(allow_macro_instructions
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H A Dassembler-a64.h62 VIXL_ASSERT(!IsValid());
63 VIXL_ASSERT(IsNone());
68 VIXL_ASSERT(IsValidOrNone());
72 VIXL_ASSERT(IsValid());
77 VIXL_ASSERT(IsValidOrNone());
82 VIXL_ASSERT(code_ < (sizeof(RegList) * 8));
87 VIXL_ASSERT(IsValid());
92 VIXL_ASSERT(IsValid());
93 VIXL_ASSERT(size() % 8 == 0);
98 VIXL_ASSERT(IsVali
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H A Dassembler-a64.cc39 VIXL_ASSERT((1 << index) & list_);
46 VIXL_ASSERT(IsValid());
52 VIXL_ASSERT((1 << index) & list_);
84 VIXL_ASSERT(type() == CPURegister::kNoRegister);
85 VIXL_ASSERT(IsEmpty());
153 VIXL_ASSERT(code < kNumberOfRegisters);
163 VIXL_ASSERT(code < kNumberOfRegisters);
170 VIXL_ASSERT(code < kNumberOfFPRegisters);
176 VIXL_ASSERT(code < kNumberOfFPRegisters);
182 VIXL_ASSERT(IsValidRegiste
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H A Dmacro-assembler-a64.cc31 VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) &&
52 VIXL_ASSERT(allow_macro_instructions_);
60 VIXL_ASSERT(allow_macro_instructions_);
67 VIXL_ASSERT(allow_macro_instructions_);
75 VIXL_ASSERT(allow_macro_instructions_);
83 VIXL_ASSERT(allow_macro_instructions_);
91 VIXL_ASSERT(allow_macro_instructions_);
99 VIXL_ASSERT(allow_macro_instructions_);
107 VIXL_ASSERT(allow_macro_instructions_);
115 VIXL_ASSERT(allow_macro_instructions
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H A Dinstructions-a64.cc36 VIXL_ASSERT(width <= 64);
46 VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
48 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
158 VIXL_ASSERT(BranchType() != UnknownBranchType);
189 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR);
198 VIXL_ASSERT(((target - this) & 3) == 0);
230 VIXL_ASSERT(((source - this) & 3) == 0);
H A Dcpu-a64.cc89 VIXL_ASSERT(CountSetBits(dsize, 64) == 1);
90 VIXL_ASSERT(CountSetBits(isize, 64) == 1);
H A Dsimulator-a64.h140 VIXL_ASSERT(size <= kSizeInBytes);
141 VIXL_ASSERT(size <= sizeof(new_value));
152 VIXL_ASSERT(size <= kSizeInBytes);
194 VIXL_ASSERT(IsWordAligned(pc_));
214 VIXL_ASSERT(size_in_bytes <= sizeof(T));
215 VIXL_ASSERT((size == kXRegSize) || (size == kWRegSize));
216 VIXL_ASSERT(code < kNumberOfRegisters);
256 VIXL_ASSERT(size_in_bytes <= sizeof(T));
257 VIXL_ASSERT((size == kXRegSize) || (size == kWRegSize));
258 VIXL_ASSERT(cod
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H A Ddecoder-a64.cc135 VIXL_ASSERT(*it == registered_visitor);
153 VIXL_ASSERT(*it == registered_visitor);
164 VIXL_ASSERT(instr->Bits(27, 24) == 0x0);
167 VIXL_ASSERT(instr->Bit(28) == 0x1);
173 VIXL_ASSERT((instr->Bits(27, 24) == 0x4) ||
274 VIXL_ASSERT((instr->Bits(27, 24) == 0x8) ||
393 VIXL_ASSERT(instr->Bits(27, 24) == 0x2);
412 VIXL_ASSERT(instr->Bits(27, 24) == 0x3);
437 VIXL_ASSERT(instr->Bits(27, 24) == 0x1);
447 VIXL_ASSERT((inst
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H A Ddebugger-a64.cc91 VIXL_ASSERT(tok->IsRegister());
113 VIXL_ASSERT(tok->IsFPRegister());
137 VIXL_ASSERT(tok->IsIdentifier());
155 VIXL_ASSERT(tok->IsAddress());
172 VIXL_ASSERT(tok->IsInteger());
199 VIXL_ASSERT(tok->IsFormat());
609 VIXL_ASSERT(count > 0);
630 VIXL_ASSERT(count > 0);
718 VIXL_ASSERT(end[1] == '\0');
719 VIXL_ASSERT((en
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H A Dsimulator-a64.cc39 VIXL_ASSERT(is_uintn(width, bits) || is_intn(width, bits));
43 VIXL_ASSERT((mask & write_ignore_mask_) == 0);
64 VIXL_ASSERT((static_cast<int32_t>(-1) >> 1) == -1);
65 VIXL_ASSERT((static_cast<uint32_t>(-1) >> 1) == 0x7FFFFFFF);
174 VIXL_ASSERT(code < kNumberOfRegisters);
184 VIXL_ASSERT(code < kNumberOfRegisters);
194 VIXL_ASSERT(code < kNumberOfFPRegisters);
200 VIXL_ASSERT(code < kNumberOfFPRegisters);
206 VIXL_ASSERT(code < kNumberOfFPRegisters);
245 VIXL_ASSERT((carry_i
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H A Ddebugger-a64.h140 VIXL_ASSERT(value > 1);
H A Dinstrument-a64.cc33 VIXL_ASSERT(name != NULL);
167 VIXL_ASSERT(counter->type() == Cumulative);
H A Dinstructions-a64.h344 VIXL_ASSERT(IsWordAligned(this + offset));
H A Ddisasm-a64.cc268 VIXL_ASSERT((reg_size == kXRegSize) ||
1187 VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT);
1255 VIXL_ASSERT(mnemonic != NULL);
1361 VIXL_ASSERT(format[0] == 'I');
1369 VIXL_ASSERT(format[5] == 'L');
1414 VIXL_ASSERT(instr->ShiftAddSub() <= 1);
1471 VIXL_ASSERT((format[0] == 'I') && (format[1] == 'B'));
1485 VIXL_ASSERT(format[3] == '-');
1491 VIXL_ASSERT((format[3] == '-') && (format[4] == 'r'));
1506 VIXL_ASSERT(strncm
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H A Dconstants-a64.h186 VIXL_ASSERT((cond != al) && (cond != nv));
293 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
/external/vixl/test/
H A Dtest-utils-a64.h43 VIXL_ASSERT(sizeof(dump_.d_[0]) == kDRegSizeInBytes);
44 VIXL_ASSERT(sizeof(dump_.s_[0]) == kSRegSizeInBytes);
45 VIXL_ASSERT(sizeof(dump_.d_[0]) == kXRegSizeInBytes);
46 VIXL_ASSERT(sizeof(dump_.s_[0]) == kWRegSizeInBytes);
47 VIXL_ASSERT(sizeof(dump_.x_[0]) == kXRegSizeInBytes);
48 VIXL_ASSERT(sizeof(dump_.w_[0]) == kWRegSizeInBytes);
65 VIXL_ASSERT(RegAliasesMatch(code));
73 VIXL_ASSERT(RegAliasesMatch(code));
79 VIXL_ASSERT(FPRegAliasesMatch(code));
88 VIXL_ASSERT(FPRegAliasesMatc
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H A Dtest-utils-a64.cc98 VIXL_ASSERT(reg.Is32Bits());
115 VIXL_ASSERT(reg.Is64Bits());
124 VIXL_ASSERT(fpreg.Is32Bits());
141 VIXL_ASSERT(fpreg.Is64Bits());
149 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
177 VIXL_ASSERT((expected & ~NZCVFlag) == 0);
178 VIXL_ASSERT((result & ~NZCVFlag) == 0);
234 VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count);
261 VIXL_ASSERT(CountSetBits(list, kNumberOfFPRegisters) == reg_count);
273 VIXL_ASSERT(!x
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H A Dtest-simulator-a64.cc124 VIXL_ASSERT(sizeof(buf) == sizeof(test_function)); \
176 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize));
177 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize));
224 VIXL_ASSERT(inputs_length > 0);
265 VIXL_ASSERT(d == expected_length);
278 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize));
336 VIXL_ASSERT(inputs_length > 0);
382 VIXL_ASSERT(d == expected_length);
395 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize));
463 VIXL_ASSERT(inputs_lengt
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H A Dcctest.cc57 VIXL_ASSERT(last_ == NULL);
H A Dtest-assembler-a64.cc175 VIXL_ASSERT(sizeof(buf) == sizeof(test_function)); \
2694 VIXL_ASSERT(range_ > 0);
2725 VIXL_ASSERT((code_size + pool_guard_size) <= range);
2739 VIXL_ASSERT(code_size == range);
4768 VIXL_ASSERT(IsSignallingNaN(s1));
4769 VIXL_ASSERT(IsSignallingNaN(s2));
4770 VIXL_ASSERT(IsSignallingNaN(sa));
4771 VIXL_ASSERT(IsQuietNaN(q1));
4772 VIXL_ASSERT(IsQuietNaN(q2));
4773 VIXL_ASSERT(IsQuietNa
8291 VIXL_ASSERT(i < reg_count); function
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H A Dtest-disasm-a64.cc1559 VIXL_ASSERT(kUnreachableOpcode == 0xdeb0);
1573 VIXL_ASSERT(kTraceOpcode == 0xdeb2);
1588 VIXL_ASSERT(kLogOpcode == 0xdeb3);
/external/vixl/src/
H A Dutils-vixl.cc61 VIXL_ASSERT((width == 32) || (width == 64));
73 VIXL_ASSERT((width == 32) || (width == 64));
83 VIXL_ASSERT((width == 32) || (width == 64));
95 VIXL_ASSERT((width == 32) || (width == 64));
H A Dglobals-vixl.h74 #define VIXL_ASSERT(condition) assert(condition) macro
75 #define VIXL_CHECK(condition) VIXL_ASSERT(condition)
84 #define VIXL_ASSERT(condition) ((void) 0) macro
H A Dutils-vixl.h38 VIXL_ASSERT((0 < n) && (n < 64));
44 VIXL_ASSERT((0 < n) && (n < 64));
49 VIXL_ASSERT((0 < n) && (n < 64));
130 VIXL_ASSERT(isnan(num));
137 VIXL_ASSERT(isnan(num));
163 VIXL_ASSERT(sizeof(pointer) == sizeof(intptr_t)); // NOLINT(runtime/sizeof)
173 VIXL_ASSERT((pointer_raw + align_step) % alignment == 0);
183 VIXL_ASSERT((pointer_raw - align_step) % alignment == 0);

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