Searched refs:VSHL (Results 1 - 10 of 10) sorted by relevance
/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
H A D | omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 276 VSHL qT0s,qShift 277 VSHL qT1s,qShift
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H A D | omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 389 VSHL qT0s,qShift 390 VSHL qT1s,qShift 398 VSHL dX0,dShift
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 110 VSHL, enumerator in enum:llvm::AArch64ISD::__anon25945
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H A D | AArch64ISelLowering.cpp | 699 case AArch64ISD::VSHL: return "AArch64ISD::VSHL"; 5041 // This will have been turned into: AArch64ISD::VSHL vector, #shift 5044 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) 5794 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 113 VSHL, // ...left enumerator in enum:llvm::ARMISD::NodeType
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H A D | ARMISelLowering.cpp | 1004 case ARMISD::VSHL: return "ARMISD::VSHL"; 3821 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3829 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 4216 // Lower vector shifts on NEON to use VSHL. 9277 VShiftOpc = ARMISD::VSHL; 9417 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 274 // VSHL, VSRL - 128-bit vector logical left / right shift 277 // VSHL, VSRL, VSRA - Vector shift elements 278 VSHL, VSRL, VSRA, enumerator in enum:llvm::X86ISD::NodeType
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H A D | X86ISelLowering.cpp | 13456 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 13957 Opcode = X86ISD::VSHL; 15510 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1)); 16564 case X86ISD::VSHL: return "X86ISD::VSHL";
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/external/valgrind/main/none/tests/arm/ |
H A D | neon128.stdout.exp | 429 ---- VSHL (register) ---- 2544 ---- VSHL (immediate) ----
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H A D | neon64.stdout.exp | 618 ---- VSHL (register) ---- 3824 ---- VSHL (immediate) ----
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