/external/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 75 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 76 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 78 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 79 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 83 Matrix[*Units].unify(VirtReg); 89 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument 90 unsigned PhysReg = VRM->getPhys(VirtReg.reg); 91 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 93 VRM->clearVirt(VirtReg 102 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 120 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 133 query(LiveInterval &VirtReg, unsigned RegUnit) argument 141 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { argument 30 if (VirtReg.empty()) 35 LiveInterval::iterator RegPos = VirtReg.begin(); 36 LiveInterval::iterator RegEnd = VirtReg.end(); 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 56 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { argument 57 if (VirtReg.empty()) 62 LiveInterval::iterator RegPos = VirtReg [all...] |
H A D | RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) { 89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); 92 if (MRI->reg_nodbg_empty(VirtReg->reg)) { 93 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); 94 LIS->removeInterval(VirtReg->reg); 105 << MRI->getRegClass(VirtReg->reg)->getName() 106 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); 109 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); 116 I = MRI->reg_instr_begin(VirtReg [all...] |
H A D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, argument 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
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H A D | RegAllocFast.cpp | 73 unsigned VirtReg; // Virtual register number. member in struct:__anon25790::RAFast::LiveReg 79 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} 82 return TargetRegisterInfo::virtReg2Index(VirtReg); 168 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 173 void killVirtReg(unsigned VirtReg); 175 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 181 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { argument 182 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 184 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { 185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 202 getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) argument 257 killVirtReg(unsigned VirtReg) argument 267 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument 500 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 511 const unsigned VirtReg = LRI->VirtReg; local 583 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 616 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument [all...] |
H A D | RegAllocBasic.cpp | 103 unsigned selectOrSplit(LiveInterval &VirtReg, 112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 165 // that interfere with VirtReg. The newly spilled or split live intervals are 167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 175 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); 181 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) 187 " interferences with " << VirtReg << "\n"); 221 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, argument 227 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 230 switch (Matrix->checkInterference(VirtReg, PhysRe [all...] |
H A D | RegAllocGreedy.cpp | 197 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 198 return ExtraRegInfo[VirtReg.reg].Stage; 201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument 203 ExtraRegInfo[VirtReg.reg].Stage = Stage; 338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, 354 unsigned calculateRegionSplitCost(LiveInterval &VirtReg, 359 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, 364 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order, 454 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { argument 464 LRE_WillShrinkVirtReg(unsigned VirtReg) argument 568 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 612 canReassign(LiveInterval &VirtReg, unsigned PrevReg) argument 675 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 757 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument 798 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit) argument 1290 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1320 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR) argument 1401 doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, bool HasCompact, SmallVectorImpl<unsigned> &NewVRegs) argument 1449 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1517 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1660 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument [all...] |
H A D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | AllocationOrder.h | 34 /// Create a new AllocationOrder for VirtReg. 35 /// @param VirtReg Virtual register to allocate for. 38 AllocationOrder(unsigned VirtReg,
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H A D | RegAllocBase.h | 83 /// enqueue - Add VirtReg to the priority queue of unassigned registers. 93 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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H A D | VirtRegMap.cpp | 83 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { argument 84 unsigned Hint = MRI->getSimpleHint(VirtReg); 89 return getPhys(VirtReg) == Hint; 92 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { argument 93 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 243 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); local 244 if (MRI->reg_nodbg_empty(VirtReg)) 246 LiveInterval &LI = LIS->getInterval(VirtReg); 251 unsigned PhysReg = VRM->getPhys(VirtReg); 327 // If we encounter a VirtReg o 338 unsigned VirtReg = MO.getReg(); local [all...] |
H A D | LiveDebugVariables.cpp | 312 /// lookupVirtReg - Find the EC leader for VirtReg or null. 313 UserValue *lookupVirtReg(unsigned VirtReg); 350 void mapVirtReg(unsigned VirtReg, UserValue *EC); 442 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument 443 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); 444 UserValue *&Leader = virtRegToEqClass[VirtReg]; 448 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument 449 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) 882 unsigned VirtReg = Loc.getReg(); local 883 if (VRM.isAssignedReg(VirtReg) [all...] |
H A D | TargetRegisterInfo.cpp | 264 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument 270 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 282 // Check that Phys is a valid hint in VirtReg's register class. 288 // from VirtReg's register class if they aren't in the allocation order. The
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H A D | InlineSpiller.cpp | 854 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument 857 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 863 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) 879 markValueUsed(&VirtReg, ParentVNI); 884 // If the instruction also writes VirtReg.reg, it had better not require the 888 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); 890 markValueUsed(&VirtReg, ParentVNI); 917 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
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H A D | MachineBasicBlock.cpp | 368 unsigned VirtReg = I->getOperand(0).getReg(); local 369 if (!MRI.constrainRegClass(VirtReg, RC)) 371 return VirtReg; 375 unsigned VirtReg = MRI.createVirtualRegister(RC); local 376 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 380 return VirtReg;
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H A D | PHIElimination.cpp | 198 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs. 200 static bool isImplicitlyDefined(unsigned VirtReg, argument 202 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
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H A D | MachineTraceMetrics.cpp | 624 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) 626 assert(TargetRegisterInfo::isVirtualRegister(VirtReg)); 627 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveRegMatrix.h | 97 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 101 /// Check for interference before assigning VirtReg to PhysReg. 102 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 107 /// Assign VirtReg to PhysReg. 108 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and 110 void assign(LiveInterval &VirtReg, unsigned PhysReg); 112 /// Unassign VirtReg from its PhysReg. 113 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes 115 void unassign(LiveInterval &VirtReg); [all...] |
H A D | LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg); 90 void extract(LiveInterval &VirtReg); 107 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query 108 LiveInterval::iterator VirtRegI; // current position in VirtReg 117 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} 120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), 126 VirtReg = nullptr; 137 if (UserTag == UTag && VirtReg == VReg && 144 VirtReg = VReg; 150 assert(VirtReg [all...] |
H A D | VirtRegMap.h | 129 /// @brief returns true if VirtReg is assigned to its preferred physreg. 130 bool hasPreferredPhys(unsigned VirtReg); 132 /// @brief returns true if VirtReg has a known preferred register. 133 /// This returns false if VirtReg has a preference that is a virtual 135 bool hasKnownPreference(unsigned VirtReg); 147 /// getOriginal - Return the original virtual register that VirtReg descends 151 unsigned getOriginal(unsigned VirtReg) const { 152 unsigned Orig = getPreSplitReg(VirtReg); 153 return Orig ? Orig : VirtReg;
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H A D | ScheduleDAGInstrs.h | 35 unsigned VirtReg; member in struct:llvm::VReg2SUnit 38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 41 return TargetRegisterInfo::virtReg2Index(VirtReg);
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H A D | RegisterPressure.h | 421 bool hasUntiedDef(unsigned VirtReg) const { 422 return UntiedDefs.count(VirtReg);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 132 void getRegAllocationHints(unsigned VirtReg,
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H A D | ARMBaseRegisterInfo.cpp | 217 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument 223 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 234 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
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/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 638 /// VirtReg. These registers are effectively moved to the front of the 641 /// The Order argument is the allocation order for VirtReg's register class 649 /// order for VirtReg. There may be target-independent hints. 650 virtual void getRegAllocationHints(unsigned VirtReg,
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